Inventor · disambiguated record
Tuong Trieu
Also filed as: TRIEU TUONG · TRIEU TUONG P
13 granted patents·2 pending applications·322 citations·filing 1995–2007
92Inventor score
Technology areasG06F
Top patents by PatentIndex Score
15 records- 0178US5925135AClock rate compensation for a low frequency slave deviceINTEL CORP·Filed 1996·Granted Jul 20, 1999·86 cites·28 claims
- 0272US6243781B1Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipeINTEL CORP·Filed 1998·Granted Jun 5, 2001·67 cites·14 claims
- 0367US5926651AOutput buffer with current paths having different current carrying characteristics for providing programmable slew rate and signal strengthINTEL CORP·Filed 1995·Granted Jul 20, 1999·51 cites·20 claims
- 0461US7230627B2Optimized memory addressingINTEL CORP·Filed 2004·Granted Jun 12, 2007·6 cites·25 claims
- 0559US7612780B2Optimized memory addressingINTEL CORP·Filed 2007·Granted Nov 3, 2009·1 cites·14 claims
- 0659US6330646B1Arbitration mechanism for a computer system having a unified memory architectureINTEL CORP·Filed 1999·Granted Dec 11, 2001·36 cites·23 claims
- 0759US6314472B1Abort of DRAM read ahead when PCI read multiple has endedINTEL CORP·Filed 1998·Granted Nov 6, 2001·34 cites·23 claims
- 0855US5898859AAddress shadow feature and methods of using the sameINTEL CORP·Filed 1996·Granted Apr 27, 1999·29 cites·25 claims
- 0947US7181605B2Deterministic shut down of memory devices in response to a system warm resetINTEL CORP·Filed 2003·Granted Feb 20, 2007·1 cites·28 claims
- 1044US7180520B2Queue partitioning mechanismINTEL CORP·Filed 2004·Granted Feb 20, 2007·0 cites·32 claims
- 1144US2005190193A1Apparatus and a method to adjust signal timing on a memory interfaceFiled 2004·Application pending·0 cites
- 1243US7797492B2Method and apparatus for dedicating cache entries to certain streams for performance optimizationMUKKER ANOOP·Filed 2004·Granted Sep 14, 2010·1 cites·25 claims
- 1343US2005198459A1Apparatus and method for open loop buffer allocationGEN ELECTRIC·Filed 2004·Application pending·0 cites
- 1433US6629217B1Method and apparatus for improving read latency for processor to system memory read transactionsINTEL CORP·Filed 1999·Granted Sep 30, 2003·6 cites·23 claims
- 1531US6237055B1Avoiding livelock when performing a long stream of transactionsINTEL CORP·Filed 1998·Granted May 22, 2001·4 cites·21 claims
Join the waitlist — get patent alerts
Get an alert when Tuong Trieu files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →