Inventor · disambiguated record
Eyal Naor
Also filed as: NAOR EYAL
19 granted patents·2 pending applications·4 citations·filing 2017–2022
88Inventor score
Files withIBM21
Top patents by PatentIndex Score
21 records- 0181US10929142B2Making precise operand-store-compare predictions to avoid false dependenciesIBM·Filed 2019·Granted Feb 23, 2021·3 cites·19 claims
- 0270US10977040B2Heuristic invalidation of non-useful entries in an arrayIBM·Filed 2019·Granted Apr 13, 2021·1 cites·20 claims
- 0365US10970214B2Selective downstream cache processing for data accessIBM·Filed 2019·Granted Apr 6, 2021·0 cites·17 claims
- 0465US10956328B2Selective downstream cache processing for data accessIBM·Filed 2019·Granted Mar 23, 2021·0 cites·19 claims
- 0564US11907124B2Using a shadow copy of a cache in a cache hierarchyIBM·Filed 2022·Granted Feb 20, 2024·0 cites·19 claims
- 0664US2019213129A1Selective downstream cache processing for data accessIBM·Filed 2019·Application pending·0 cites
- 0761US10409724B2Selective downstream cache processing for data accessIBM·Filed 2017·Granted Sep 10, 2019·0 cites·4 claims
- 0860US10417127B2Selective downstream cache processing for data accessIBM·Filed 2017·Granted Sep 17, 2019·0 cites·12 claims
- 0960US10360030B2Efficient pointer load and formatIBM·Filed 2017·Granted Jul 23, 2019·0 cites·5 claims
- 1059US10353707B2Efficient pointer load and formatIBM·Filed 2017·Granted Jul 16, 2019·0 cites·10 claims
- 1159US10169041B1Efficient pointer load and formatIBM·Filed 2017·Granted Jan 1, 2019·0 cites·1 claims
- 1251US11029950B2Reducing latency of common source data movement instructionsIBM·Filed 2019·Granted Jun 8, 2021·0 cites·20 claims
- 1349US11144321B2Store hit multiple load side register for preventing a subsequent store memory violationIBM·Filed 2019·Granted Oct 12, 2021·0 cites·14 claims
- 1448US10691604B2Minimizing cache latencies using set predictorsIBM·Filed 2017·Granted Jun 23, 2020·0 cites·16 claims
- 1547US10684951B2Minimizing cache latencies using set predictorsIBM·Filed 2017·Granted Jun 16, 2020·0 cites·3 claims
- 1647US10678549B2Executing processor instructions using minimal dependency queueIBM·Filed 2017·Granted Jun 9, 2020·0 cites·17 claims
- 1747US10649777B2Hardware-based data prefetching based on loop-unrolled instructionsIBM·Filed 2018·Granted May 12, 2020·0 cites·14 claims
- 1842US11157281B2Prefetching data based on register-activity patternsIBM·Filed 2018·Granted Oct 26, 2021·0 cites·18 claims
- 1942US10572624B2Modified design debugging using differential trace backIBM·Filed 2018·Granted Feb 25, 2020·0 cites·20 claims
- 2040US10324815B2Error checking of a multi-threaded computer processor design under testIBM·Filed 2017·Granted Jun 18, 2019·0 cites·20 claims
- 2137US2019310856A1Executing instructions based on a shared physical registerIBM·Filed 2018·Application pending·0 cites
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