Inventor · disambiguated record
Ronald K. Sampson
Also filed as: SAMPSON RONALD · SAMPSON RONALD K · SAMPSON RONALD KEVIN
16 granted patents·199 citations·filing 1992–2020
92Inventor score
Top patents by PatentIndex Score
16 records- 0193US8476765B2Copper interconnect structure having a graphene capZHANG JOHN HONGGUANG·Filed 2010·Granted Jul 2, 2013·24 cites·25 claims
- 0291US8569899B2Device and method for alignment of vertically stacked wafers and dieZHANG JOHN H·Filed 2009·Granted Oct 29, 2013·14 cites·17 claims
- 0389US6424137B1Use of acoustic spectral analysis for monitoring/control of CMP processesST MICROELECTRONICS INC·Filed 2000·Granted Jul 23, 2002·42 cites·20 claims
- 0483US9601382B2Method for the formation of a FinFET device with epitaxially grown source-drain regions having a reduced leakage pathST MICROELECTRONICS INC·Filed 2015·Granted Mar 21, 2017·3 cites·25 claims
- 0581US9601381B2Method for the formation of a finFET device with epitaxially grown source-drain regions having a reduced leakage pathST MICROELECTRONICS INC·Filed 2013·Granted Mar 21, 2017·4 cites·23 claims
- 0677US5313044AMethod and apparatus for real-time wafer temperature and thin film growth measurement and control in a lamp-heated rapid thermal processorUNIV DUKE·Filed 1992·Granted May 17, 1994·78 cites·9 claims
- 0771US11205621B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2020·Granted Dec 21, 2021·0 cites·12 claims
- 0869US9324660B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2013·Granted Apr 26, 2016·1 cites·13 claims
- 0968US9136384B2Method for the formation of a FinFET device having partially dielectric isolated Fin structureST MICROELECTRONICS INC·Filed 2013·Granted Sep 15, 2015·1 cites·22 claims
- 1060US10615125B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2017·Granted Apr 7, 2020·0 cites·12 claims
- 1157US9870999B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2015·Granted Jan 16, 2018·0 cites·23 claims
- 1255US10199392B2FinFET device having a partially dielectric isolated fin structureST MICROELECTRONICS INC·Filed 2016·Granted Feb 5, 2019·0 cites·23 claims
- 1355US9385051B2Method for the formation of a FinFET device having partially dielectric isolated fin structureST MICROELECTRONICS INC·Filed 2015·Granted Jul 5, 2016·0 cites·23 claims
- 1452US6022788AMethod of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed therebyST MICROELECTRONICS INC·Filed 1997·Granted Feb 8, 2000·18 cites·33 claims
- 1550US8560111B2Method of determining pressure to apply to wafers during a CMPZHANG JOHN H·Filed 2009·Granted Oct 15, 2013·0 cites·16 claims
- 1648US6087709AMethod of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed therebyST MICROELECTRONICS INC·Filed 1999·Granted Jul 11, 2000·14 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →