Inventor · disambiguated record
Mosur K. Ravishankar
Also filed as: RAVISHANKAR MOSUR K · RAVISHANKAR MOSUR KUMARASWAMY
12 granted patents·637 citations·filing 2001–2012
94Inventor score
Top patents by PatentIndex Score
12 records- 0195US6697919B2System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Feb 24, 2004·108 cites·3 claims
- 0294US6622217B2Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Sep 16, 2003·114 cites·16 claims
- 0393US8744856B1Computer implemented system and method and computer program product for evaluating pronunciation of phonemes in a languageRAVISHANKAR MOSUR K·Filed 2012·Granted Jun 3, 2014·45 cites·23 claims
- 0493US6675265B2Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participantsHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jan 6, 2004·93 cites·14 claims
- 0592US6636949B2System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessingHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Oct 21, 2003·80 cites·41 claims
- 0689US6640287B2Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requestsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Oct 28, 2003·60 cites·41 claims
- 0785US6751720B2Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchyHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jun 15, 2004·42 cites·15 claims
- 0880US6748498B2Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vectorHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jun 8, 2004·31 cites·49 claims
- 0976US6751710B2Scalable multiprocessor system and cache coherence methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jun 15, 2004·23 cites·54 claims
- 1072US6622218B2Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 16, 2003·18 cites·60 claims
- 1169US7389389B2System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jun 17, 2008·12 cites·17 claims
- 1266US6925537B2Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participantsHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Aug 2, 2005·11 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →