Inventor · disambiguated record
Clarence K. Coffee
Also filed as: COFFEE CLARENCE · COFFEE CLARENCE K · COFFEE CLARENCE KEVIN
11 granted patents·1 pending application·290 citations·filing 1998–2021
91Inventor score
Files withCOMPAQ COMPUTER CORP6MOTOROLA SOLUTIONS INC3COMPAQ INFORMATION TECHNOLOGIE1FREESCALE SEMICONDUCTOR INC1MOTOROLA INC1
Top patents by PatentIndex Score
12 records- 0190US10491235B1Devices and methods for multi-mode sample generationMOTOROLA SOLUTIONS INC·Filed 2018·Granted Nov 26, 2019·9 cites·18 claims
- 0284US6356972B1System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefromCOMPAQ INFORMATION TECHNOLOGIE·Filed 2001·Granted Mar 12, 2002·34 cites·17 claims
- 0376US6160562ASystem and method for aligning an initial cache line of data read from local memory by an input/output deviceCOMPAQ COMPUTER CORP·Filed 1998·Granted Dec 12, 2000·73 cites·18 claims
- 0474US6202101B1System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefromCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 13, 2001·58 cites·10 claims
- 0572US6272651B1System and method for improving processor read latency in a system employing error checking and correctionCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 7, 2001·61 cites·19 claims
- 0669US7376777B2Performing an N-bit write access to an M×N-bit-only peripheralFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted May 20, 2008·5 cites·20 claims
- 0759US11653193B1Communication system and method for controlling access to portable radio public safety service applicationsMOTOROLA SOLUTIONS INC·Filed 2021·Granted May 16, 2023·0 cites·31 claims
- 0851US6209052B1System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiterCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 27, 2001·23 cites·18 claims
- 0950US12120516B2Dynamically enabling a security feature of a wireless communication device based on environmental contextMOTOROLA SOLUTIONS INC·Filed 2021·Granted Oct 15, 2024·0 cites·20 claims
- 1043US6199118B1System and method for aligning an initial cache line of data read from an input/output device by a central processing unitCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 6, 2001·15 cites·18 claims
- 1140US6216190B1System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral busCOMPAQ COMPUTER CORP·Filed 1998·Granted Apr 10, 2001·12 cites·22 claims
- 1231US2006148430A1Power management of a transmitter and supporting methods and apparatusMOTOROLA INC·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →