Inventor · disambiguated record
Jiann-Cherng Lan
Also filed as: LAN JIANN-CHERNG · LAN JIANN-CHERNG JAMES
9 granted patents·55 citations·filing 1999–2002
85Inventor score
Files withINTEL CORP9
Top patents by PatentIndex Score
9 records- 0166US6631093B2Low power precharge scheme for memory bit linesINTEL CORP·Filed 2001·Granted Oct 7, 2003·16 cites·24 claims
- 0263US6629194B2Method and apparatus for low power memory bit line prechargeINTEL CORP·Filed 2001·Granted Sep 30, 2003·11 cites·17 claims
- 0362US6833735B2Single stage pulsed domino circuit for driving cascaded skewed static logic circuitsINTEL CORP·Filed 2002·Granted Dec 21, 2004·11 cites·14 claims
- 0448US6124737ALow power clock buffer having a reduced, clocked, pull-down transistorINTEL CORP·Filed 1999·Granted Sep 26, 2000·9 cites·18 claims
- 0540US6628539B2Multi-entry register cellINTEL CORP·Filed 2001·Granted Sep 30, 2003·0 cites·24 claims
- 0639US6127850ALow power clock buffer with shared, clocked transistorINTEL CORP·Filed 1999·Granted Oct 3, 2000·5 cites·18 claims
- 0738US6369616B1Low power clock buffer with shared, precharge transistorINTEL CORP·Filed 2000·Granted Apr 9, 2002·1 cites·15 claims
- 0832US6111435ALow power multiplexer with shared, clocked transistorINTEL CORP·Filed 1999·Granted Aug 29, 2000·2 cites·18 claims
- 0930US6341099B1Reducing power consumption in a data storage deviceINTEL CORP·Filed 2000·Granted Jan 22, 2002·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →