Inventor · disambiguated record
Michael Espig
Also filed as: ESPIG MICHAEL · ESPIG MICHAEL J
24 granted patents·18 pending applications·197 citations·filing 2008–2024
95Inventor score
Top patents by PatentIndex Score
42 records- 0199US11748103B2Systems and methods for performing matrix compress and decompress instructionsINTEL CORP·Filed 2022·Granted Sep 5, 2023·9 cites·20 claims
- 0299US11249761B2Systems and methods for performing matrix compress and decompress instructionsINTEL CORP·Filed 2020·Granted Feb 15, 2022·11 cites·24 claims
- 0399US10719323B2Systems and methods for performing matrix compress and decompress instructionsINTEL CORP·Filed 2018·Granted Jul 21, 2020·56 cites·20 claims
- 0498US11847185B2Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elementsINTEL CORP·Filed 2021·Granted Dec 19, 2023·7 cites·21 claims
- 0598US11507376B2Systems for performing instructions for fast element unpacking into 2-dimensional registersINTEL CORP·Filed 2021·Granted Nov 22, 2022·10 cites·24 claims
- 0698US10896043B2Systems for performing instructions for fast element unpacking into 2-dimensional registersINTEL CORP·Filed 2018·Granted Jan 19, 2021·34 cites·20 claims
- 0796US10922077B2Apparatuses, methods, and systems for stencil configuration and computation instructionsINTEL CORP·Filed 2018·Granted Feb 16, 2021·23 cites·24 claims
- 0895US10942985B2Apparatuses, methods, and systems for fast fourier transform configuration and computation instructionsINTEL CORP·Filed 2018·Granted Mar 9, 2021·25 cites·24 claims
- 0993US12175246B2Systems and methods for performing matrix compress and decompress instructionsINTEL CORP·Filed 2023·Granted Dec 24, 2024·1 cites·18 claims
- 1092US11294671B2Systems and methods for performing duplicate detection instructions on 2D dataINTEL CORP·Filed 2018·Granted Apr 5, 2022·8 cites·25 claims
- 1191US12287843B2Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elementsINTEL CORP·Filed 2023·Granted Apr 29, 2025·1 cites·20 claims
- 1291US11886875B2Systems and methods for performing nibble-sized operations on matrix elementsINTEL CORP·Filed 2018·Granted Jan 30, 2024·7 cites·19 claims
- 1386US2025199812A1Systems and methods for performing matrix compress and decompress instructionsINTEL CORP·Filed 2024·Application pending·0 cites
- 1471US11836464B2Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuitsINTEL CORP·Filed 2022·Granted Dec 5, 2023·0 cites·17 claims
- 1570US8762599B2Delegating a poll operation to another deviceINTEL CORP·Filed 2012·Granted Jun 24, 2014·2 cites·16 claims
- 1665US8553693B2Network controller circuitry to issue at least one portion of packet payload to device in manner that by-passes communication protocol stack involvementWANG REN·Filed 2010·Granted Oct 8, 2013·2 cites·18 claims
- 1764US11366636B2Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuitsINTEL CORP·Filed 2020·Granted Jun 21, 2022·0 cites·20 claims
- 1860US2020210517A1Systems and methods to accelerate multiplication of sparse matricesINTEL CORP·Filed 2018·Application pending·0 cites
- 1956US8495464B2Reliability support in memory systems without error correcting code supportSTRACOVSKY HENRY·Filed 2010·Granted Jul 23, 2013·1 cites·14 claims
- 2055US12321714B2Compressed wallace trees in FMA circuitsINTEL CORP·Filed 2021·Granted Jun 3, 2025·0 cites·21 claims
- 2155US12099838B2Instruction and logic for sum of square differencesINTEL CORP·Filed 2020·Granted Sep 24, 2024·0 cites·17 claims
- 2255US8364862B2Delegating a poll operation to another deviceINTEL CORP·Filed 2009·Granted Jan 29, 2013·0 cites·17 claims
- 2353US11327754B2Method and apparatus for approximation using polynomialsINTEL CORP·Filed 2019·Granted May 10, 2022·0 cites·20 claims
- 2453US10713012B2Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuitsINTEL CORP·Filed 2018·Granted Jul 14, 2020·0 cites·24 claims
- 2553US2025004764A1Support for less than 512-bit operand processingINTEL CORP·Filed 2023·Application pending·0 cites
- 2652US2025004768A1Vector packed matrix multiplication and accumulation processors, methods, systems, and instructionsHEINECKE ALEXANDER·Filed 2023·Application pending·0 cites
- 2752US2025028533A1Zero-clearing scalar movesINTEL CORP·Filed 2023·Application pending·0 cites
- 2852US2024220248A1Restricting vector length in a processorINTEL CORP·Filed 2022·Application pending·0 cites
- 2950US12182570B2Apparatuses, methods, and systems for a packed data convolution instruction with shift control and width controlINTEL CORP·Filed 2021·Granted Dec 31, 2024·0 cites·24 claims
- 3050US2024103865A1Vector multiply-add/subtract with intermediate roundingESPIG MICHAEL·Filed 2023·Application pending·0 cites
- 3149US2024004648A1Vector unpack based on selection informationINTEL CORP·Filed 2022·Application pending·0 cites
- 3249US2024103872A1Truncation floating-point conversion to integer with saturationMORGAN JOHN·Filed 2023·Application pending·0 cites
- 3349US2012189204A1Linking Disparate Content SourcesJOHNSON BRIAN D·Filed 2009·Application pending·0 cites
- 3448US2010169519A1Reconfigurable buffer managerZHANG YONG·Filed 2008·Application pending·0 cites
- 3546US2020210172A1Dynamic configuration of a data flow array for processing data flow array instructionsINTEL CORP·Filed 2018·Application pending·0 cites
- 3645US2024004662A1Instructions and support for horizontal reductionsINTEL CORP·Filed 2022·Application pending·0 cites
- 3745US2011123117A1Searching and Extracting Digital Images From Digital Video FilesJOHNSON BRIAN D·Filed 2009·Application pending·0 cites
- 3845US2020210188A1Systems and methods for performing matrix row- and column-wise permute instructionsINTEL CORP·Filed 2018·Application pending·0 cites
- 3945US2023185873A1Method and apparatus for separable convolution filter operations on matrix multiplication arraysINTEL CORP·Filed 2021·Application pending·0 cites
- 4044US2022308881A1Instruction and logic for sum of absolute differencesINTEL CORP·Filed 2021·Application pending·0 cites
- 4143US2023161941A1Application negotiable platform thermal aware schedulerINTEL CORP·Filed 2021·Application pending·0 cites
- 4242US8649262B2Dynamic configuration of potential links between processing elementsSRINIVASAN SADAGOPAN·Filed 2008·Granted Feb 11, 2014·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →