Inventor · disambiguated record
Peter Labrecque
Also filed as: LABRECQUE PETER · LABRECQUE PETER N · LABRECQUE PETER NORMAND
4 granted patents·1 pending application·13 citations·filing 2001–2019
69Inventor score
Technology areasG11C
Top patents by PatentIndex Score
5 records- 0170US8305835B2Memory elements having configurable access duty cycles and related operating methodsSCHREIBER RUSSELL·Filed 2010·Granted Nov 6, 2012·6 cites·20 claims
- 0259US10878891B1SRAM bitcell supply block with multiple operating modesSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Dec 29, 2020·2 cites·21 claims
- 0352US10008257B2Memory bitcell with column selectORACLE INT CORP·Filed 2015·Granted Jun 26, 2018·1 cites·10 claims
- 0431US6434071B1Circuit and method of selectively activating feedback devices for local bit lines in a memoryIBM·Filed 2001·Granted Aug 13, 2002·4 cites·17 claims
- 0530US2006245240A1Method and apparatus for reducing time delay through static bitlines of a static memoryIBM·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →