Inventor · disambiguated record
Tomasz Brozek
Also filed as: BROZEK TOMASZ · BROZEK TOMASZ W
90 granted patents·1 pending application·386 citations·filing 2007–2023
99Inventor score
Top patents by PatentIndex Score
91 records- 0199US7592827B1Apparatus and method for electrical detection and localization of shorts in metal interconnect linesPDF SOLUTIONS INC·Filed 2007·Granted Sep 22, 2009·114 cites·8 claims
- 0298US10593604B1Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Mar 17, 2020·19 cites·19 claims
- 0398US9870962B1Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Jan 16, 2018·13 cites·19 claims
- 0498US9799575B2Integrated circuit containing DOEs of NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Oct 24, 2017·19 cites·11 claims
- 0597US9805994B1Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such padsPDF SOLUTIONS INC·Filed 2016·Granted Oct 31, 2017·15 cites·18 claims
- 0697US9627370B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Apr 18, 2017·15 cites·20 claims
- 0797US8575955B1Apparatus and method for electrical detection and localization of shorts in metal interconnect linesBROZEK TOMASZ·Filed 2011·Granted Nov 5, 2013·88 cites·7 claims
- 0896US10978438B1IC with test structures and E-beam pads embedded within a contiguous standard cell areaPDF SOLUTIONS INC·Filed 2019·Granted Apr 13, 2021·9 cites·14 claims
- 0993US10768222B1Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structurePDF SOLUTIONS INC·Filed 2018·Granted Sep 8, 2020·13 cites·20 claims
- 1093US9741703B1Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Aug 22, 2017·4 cites·20 claims
- 1193US9691672B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Jun 27, 2017·4 cites·20 claims
- 1293US9627371B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Apr 18, 2017·7 cites·20 claims
- 1392US7935965B1Test structures and methods for electrical characterization of alignment of line patterns defined with double patterningPDF SOLUTIONS INC·Filed 2008·Granted May 3, 2011·18 cites·13 claims
- 1490US10199288B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areasPDF SOLUTIONS INC·Filed 2018·Granted Feb 5, 2019·2 cites·20 claims
- 1590US10199283B1Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stagePDF SOLUTIONS INC·Filed 2017·Granted Feb 5, 2019·3 cites·20 claims
- 1690US9905487B1Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opensPDF SOLUTIONS INC·Filed 2016·Granted Feb 27, 2018·3 cites·10 claims
- 1789US9786648B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Oct 10, 2017·2 cites·20 claims
- 1889US9773773B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Sep 26, 2017·2 cites·20 claims
- 1989US9761575B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Sep 12, 2017·2 cites·20 claims
- 2087US10290552B1Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stagePDF SOLUTIONS INC·Filed 2018·Granted May 14, 2019·2 cites·20 claims
- 2187US10199294B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stagePDF SOLUTIONS INC·Filed 2018·Granted Feb 5, 2019·1 cites·20 claims
- 2287US9761573B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Sep 12, 2017·2 cites·20 claims
- 2386US10096530B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Oct 9, 2018·4 cites·14 claims
- 2485US9947601B1Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Apr 17, 2018·1 cites·19 claims
- 2584US9922968B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Mar 20, 2018·1 cites·23 claims
- 2684US9773774B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Sep 26, 2017·4 cites·17 claims
- 2784US9721937B1Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Aug 1, 2017·1 cites·23 claims
- 2883US9653446B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted May 16, 2017·2 cites·20 claims
- 2980US9911649B1Process for making and using mesh-style NCEM padsPDF SOLUTIONS INC·Filed 2016·Granted Mar 6, 2018·2 cites·3 claims
- 3080US9728553B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Aug 8, 2017·1 cites·20 claims
- 3179US9831141B1Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Nov 28, 2017·1 cites·20 claims
- 3279US9711421B1Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted Jul 18, 2017·1 cites·20 claims
- 3376US9929063B1Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Mar 27, 2018·2 cites·19 claims
- 3476US9768083B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Sep 19, 2017·2 cites·16 claims
- 3576US9646961B1Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cellsPDF SOLUTIONS INC·Filed 2016·Granted May 9, 2017·1 cites·20 claims
- 3674US10199284B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and chamfer short test areasPDF SOLUTIONS INC·Filed 2018·Granted Feb 5, 2019·0 cites·20 claims
- 3773US10109539B1Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Oct 23, 2018·0 cites·19 claims
- 3873US9922890B1Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Mar 20, 2018·0 cites·19 claims
- 3973US9911669B1Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Mar 6, 2018·0 cites·19 claims
- 4073US9911668B1Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Mar 6, 2018·0 cites·19 claims
- 4173US9911670B1Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatePDF SOLUTIONS INC·Filed 2017·Granted Mar 6, 2018·0 cites·19 claims
- 4273US9899276B1Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Feb 20, 2018·0 cites·19 claims
- 4373US9881843B1Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesPDF SOLUTIONS INC·Filed 2017·Granted Jan 30, 2018·0 cites·19 claims
- 4472US10269786B1Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Apr 23, 2019·0 cites·19 claims
- 4572US10211112B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areasPDF SOLUTIONS INC·Filed 2018·Granted Feb 19, 2019·0 cites·20 claims
- 4672US10199289B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areasPDF SOLUTIONS INC·Filed 2018·Granted Feb 5, 2019·0 cites·20 claims
- 4772US10199287B1Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areasPDF SOLUTIONS INC·Filed 2018·Granted Feb 5, 2019·0 cites·20 claims
- 4872US10096529B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Oct 9, 2018·0 cites·20 claims
- 4972US9929136B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Mar 27, 2018·0 cites·21 claims
- 5072US9871028B1Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cellsPDF SOLUTIONS INC·Filed 2017·Granted Jan 16, 2018·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →