Inventor · disambiguated record
Choong Kit Wong
Also filed as: WONG CHOONG KIT
10 granted patents·82 citations·filing 2001–2016
86Inventor score
Top patents by PatentIndex Score
10 records- 0191US7180329B1Low-jitter adjustable level shifter with native devices and kickerALTERA CORP·Filed 2005·Granted Feb 20, 2007·35 cites·20 claims
- 0283US7265587B1LVDS output buffer pre-emphasis methods and apparatusALTERA CORP·Filed 2005·Granted Sep 4, 2007·12 cites·19 claims
- 0383US6489817B1Clock divider using positive and negative edge triggered state machinesALTERA CORP·Filed 2001·Granted Dec 3, 2002·28 cites·43 claims
- 0460US10110225B1Integrated circuit with an increased signal bandwidth input/output (I/O) circuitINTEL CORP·Filed 2016·Granted Oct 23, 2018·1 cites·15 claims
- 0560US9793888B2Techniques for enabling and disabling transistor legs in an output driver circuitALTERA CORP·Filed 2016·Granted Oct 17, 2017·1 cites·17 claims
- 0656US8151224B1Method of designing integrated circuits including providing an option to select a mask layer setANG BOON JIN·Filed 2008·Granted Apr 3, 2012·2 cites·16 claims
- 0752US8686758B1Integrated circuit with configurable I/O transistor arrangementSIA KET CHIEW·Filed 2009·Granted Apr 1, 2014·3 cites·24 claims
- 0840US7787314B2Dynamic real-time delay characterization and configurationALTERA CORP·Filed 2008·Granted Aug 31, 2010·0 cites·18 claims
- 0937US10103627B2Packaged integrated circuit including a switch-mode regulator and method of forming the sameALTERA CORP·Filed 2015·Granted Oct 16, 2018·0 cites·20 claims
- 1034US10224911B1Dual signal protocol input/output (I/O) buffer circuitALTERA CORP·Filed 2016·Granted Mar 5, 2019·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →