Inventor · disambiguated record
Xi Zhang
Also filed as: ZHANG XI · Zhang xi wei
16 granted patents·46 citations·filing 2012–2020
89Inventor score
Top patents by PatentIndex Score
16 records- 0192US10365193B2Test apparatus and method for determining time-dependence failure under constant temperature through high pressure true triaxial loading for hard rockUNIV NORTHEASTERN·Filed 2017·Granted Jul 30, 2019·8 cites·9 claims
- 0289US10324014B2Low-frequency disturbance and high-speed impact type high-pressure true triaxial test apparatus and methodUNIV NORTHEASTERN·Filed 2017·Granted Jun 18, 2019·6 cites·5 claims
- 0383US9542992B2SRAM core cell design with write assistNVIDIA CORP·Filed 2013·Granted Jan 10, 2017·9 cites·18 claims
- 0483US8866528B2Dual flip-flop circuitNVIDIA CORP·Filed 2012·Granted Oct 21, 2014·7 cites·19 claims
- 0581US10428654B2Cutter head for microwave presplitting type hard-rock tunnel boring machineUNIV NORTHEASTERN·Filed 2017·Granted Oct 1, 2019·8 cites·8 claims
- 0678US9110141B2Flip-flop circuit having a reduced hold time requirement for a scan inputNVIDIA CORP·Filed 2012·Granted Aug 18, 2015·4 cites·17 claims
- 0763US9071240B2Low power, single-rail level shifters employing power down signal from output power domain and a method of converting a data signal between power domainsNVIDIA CORP·Filed 2012·Granted Jun 30, 2015·2 cites·20 claims
- 0859US11294631B2Full adder cell with improved power efficiencyNVIDIA CORP·Filed 2019·Granted Apr 5, 2022·0 cites·20 claims
- 0958US11169779B2Full adder cell with improved power efficiencyNVIDIA CORP·Filed 2020·Granted Nov 9, 2021·0 cites·19 claims
- 1058US9525401B2Low clocking power flip-flopNVIDIA CORP·Filed 2015·Granted Dec 20, 2016·1 cites·20 claims
- 1156US8988123B2Small area low power data retention flopNVIDIA CORP·Filed 2012·Granted Mar 24, 2015·1 cites·8 claims
- 1248US9219480B2Low tau synchronizer flip-flop with dual loop feedback approach to improve mean time between failureNVIDIA CORP·Filed 2014·Granted Dec 22, 2015·0 cites·20 claims
- 1344US10931266B2Low power flip-flop element with gated clockNVIDIA CORP·Filed 2014·Granted Feb 23, 2021·0 cites·22 claims
- 1438US9842631B2Mitigating external influences on long signal linesNVIDIA CORP·Filed 2012·Granted Dec 12, 2017·0 cites·17 claims
- 1536US10116586B2Managing network bandwidth for network applicationsTENCENT TECH SHENZHEN CO LTD·Filed 2015·Granted Oct 30, 2018·0 cites·18 claims
- 1634US10181842B2Mixed threshold flip-flop element to mitigate hold time penalty due to clock distortionNVIDIA CORP·Filed 2015·Granted Jan 15, 2019·0 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →