Inventor · disambiguated record
Daniel James Dechene
Also filed as: DECHENE DANIEL · DECHENE DANIEL J · DECHENE DANIEL JAMES
23 granted patents·4 pending applications·58 citations·filing 2013–2022
92Inventor score
Top patents by PatentIndex Score
27 records- 0197US8656322B1Fin design level mask decomposition for directed self assemblyIBM·Filed 2013·Granted Feb 18, 2014·27 cites·20 claims
- 0294US11515427B2Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitanceIBM·Filed 2020·Granted Nov 29, 2022·4 cites·13 claims
- 0394US9252022B1Patterning assist feature to mitigate reactive ion etch microloading effectIBM·Filed 2014·Granted Feb 2, 2016·17 cites·19 claims
- 0487US10998193B1Spacer-assisted lithographic double patterningIBM·Filed 2020·Granted May 4, 2021·2 cites·17 claims
- 0582US10170309B2Dummy pattern addition to improve CD uniformityGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 1, 2019·3 cites·5 claims
- 0680US10833160B1Field-effect transistors with self-aligned and non-self-aligned contact openingsGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 10, 2020·3 cites·9 claims
- 0776US9780002B1Threshold voltage and well implantation method for semiconductor devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 3, 2017·2 cites·20 claims
- 0868US12080559B2Using a same mask for direct print and self-aligned double patterning of nanosheetsIBM·Filed 2021·Granted Sep 3, 2024·0 cites·20 claims
- 0965US12068415B2Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitanceIBM·Filed 2022·Granted Aug 20, 2024·0 cites·11 claims
- 1065US11888048B2Gate oxide for nanosheet transistor devicesIBM·Filed 2021·Granted Jan 30, 2024·0 cites·20 claims
- 1163US12363965B2Stacked transistor layout for improved cell height scalingIBM·Filed 2022·Granted Jul 15, 2025·0 cites·20 claims
- 1259US11977614B2Circuit design watermarkingIBM·Filed 2021·Granted May 7, 2024·0 cites·20 claims
- 1359US11257681B2Using a same mask for direct print and self-aligned double patterning of nanosheetsIBM·Filed 2019·Granted Feb 22, 2022·0 cites·20 claims
- 1459US11211474B2Gate oxide for nanosheet transistor devicesIBM·Filed 2020·Granted Dec 28, 2021·0 cites·20 claims
- 1553US12400871B2Metal lines with low via-to-via spacingIBM·Filed 2020·Granted Aug 26, 2025·0 cites·16 claims
- 1653US2023369217A1Buried via-to-backside power rail (vbpr) for stacked field-effect transistor (fet)IBM·Filed 2022·Application pending·0 cites
- 1751US11024551B1Metal replacement vertical interconnections for buried capacitanceIBM·Filed 2020·Granted Jun 1, 2021·0 cites·20 claims
- 1850US11830778B2Back-side wafer modificationIBM·Filed 2020·Granted Nov 28, 2023·0 cites·10 claims
- 1948US11527434B2Line cut patterning using sacrificial materialIBM·Filed 2020·Granted Dec 13, 2022·0 cites·20 claims
- 2048US11158536B2Patterning line cuts before line patterning using sacrificial fill materialIBM·Filed 2020·Granted Oct 26, 2021·0 cites·20 claims
- 2146US10332745B2Dummy assist features for pattern supportGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 25, 2019·0 cites·17 claims
- 2246US2021305152A1Inverted, self-aligned top-via structuresIBM·Filed 2020·Application pending·0 cites
- 2345US2021280457A1Self-aligned block via patterning for dual damascene double patterned metal linesIBM·Filed 2020·Application pending·0 cites
- 2444US2015234974A1Multiple patterning design with reduced complexitySAMSUNG ELECTRONICS CO LTD·Filed 2014·Application pending·0 cites
- 2543US10867912B2Dummy fill scheme for use with passive devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Dec 15, 2020·0 cites·16 claims
- 2643US10691862B2Layouts for connecting contacts with metal tabs or viasGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 23, 2020·0 cites·20 claims
- 2738US10217633B2Substantially defect-free polysilicon gate arraysGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 26, 2019·0 cites·12 claims
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