Inventor · disambiguated record
Serafino Bueti
Also filed as: BUETI SERAFINO
20 granted patents·8 pending applications·116 citations·filing 2004–2008
94Inventor score
Top patents by PatentIndex Score
28 records- 0191US7483806B1Design structures, method and systems of powering on integrated circuitIBM·Filed 2007·Granted Jan 27, 2009·23 cites·16 claims
- 0282US7643591B2Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical designIBM·Filed 2006·Granted Jan 5, 2010·10 cites·20 claims
- 0380US7941772B2Dynamic critical path detector for digital logic circuit pathsIBM·Filed 2007·Granted May 10, 2011·10 cites·22 claims
- 0480US7308668B2Apparatus and method for implementing an integrated circuit IP core library architectureIBM·Filed 2005·Granted Dec 11, 2007·12 cites·15 claims
- 0579US7716007B2Design structures of powering on integrated circuitIBM·Filed 2008·Granted May 11, 2010·8 cites·7 claims
- 0678US7519941B2Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitryIBM·Filed 2006·Granted Apr 14, 2009·5 cites·16 claims
- 0777US7823107B2Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical designIBM·Filed 2007·Granted Oct 26, 2010·8 cites·20 claims
- 0873US8132136B2Dynamic critical path detector for digital logic circuit pathsBUETI SERAFINO·Filed 2007·Granted Mar 6, 2012·7 cites·20 claims
- 0971US8347019B2Structure for hardware assisted bus state transition circuit using content addressable memoriesIBM·Filed 2008·Granted Jan 1, 2013·5 cites·25 claims
- 1069US8291357B2On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variationsBUETI SERAFINO·Filed 2007·Granted Oct 16, 2012·5 cites·20 claims
- 1169US7823017B2Structure for task based debugger (transaction-event-job-trigger)IBM·Filed 2008·Granted Oct 26, 2010·4 cites·14 claims
- 1265US7511548B2Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock treesIBM·Filed 2006·Granted Mar 31, 2009·3 cites·18 claims
- 1362US7594140B2Task based debugger (transaction-event-job-trigger)IBM·Filed 2006·Granted Sep 22, 2009·2 cites·16 claims
- 1461US7479819B2Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock treesIBM·Filed 2006·Granted Jan 20, 2009·2 cites·15 claims
- 1560US8016482B2Method and systems of powering on integrated circuitIBM·Filed 2007·Granted Sep 13, 2011·4 cites·14 claims
- 1658US7313738B2System and method for system-on-chip interconnect verificationIBM·Filed 2005·Granted Dec 25, 2007·1 cites·12 claims
- 1756US7865789B2System and method for system-on-chip interconnect verificationIBM·Filed 2007·Granted Jan 4, 2011·2 cites·18 claims
- 1854US7129821B2Communication systems and methods using microelectronics power distribution networkIBM·Filed 2004·Granted Oct 31, 2006·3 cites·20 claims
- 1953US7275011B2Method and apparatus for monitoring integrated circuit temperature through deterministic path delaysIBM·Filed 2005·Granted Sep 25, 2007·2 cites·16 claims
- 2048US2009094566A1Design structure for chip identification systemIBM·Filed 2008·Application pending·0 cites
- 2148US2009132747A1Structure for universal peripheral processor system for soc environments on an integrated circuitIBM·Filed 2008·Application pending·0 cites
- 2248US2008229265A1Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock TreesIBM·Filed 2008·Application pending·0 cites
- 2348US2008229266A1Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock TreesIBM·Filed 2008·Application pending·0 cites
- 2447US2009132732A1Universal peripheral processor system for soc environments on an integrated circuitIBM·Filed 2007·Application pending·0 cites
- 2545US2008183941A1Hardware assisted bus state transition using content addressable memories.IBM·Filed 2007·Application pending·0 cites
- 2645US2006041705A1System and method for arbitration between shared peripheral core devices in system on chip architecturesIBM·Filed 2004·Application pending·0 cites
- 2740US8234104B2Simulation of digital circuitsBERGKVIST JR JOHN JOSEPH·Filed 2008·Granted Jul 31, 2012·0 cites·20 claims
- 2839US2005265462A1Method and apparatus for dynamically managing power consumptions of sending and receiving driversIBM·Filed 2004·Application pending·0 cites
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