Inventor · disambiguated record
Hung Q. Le
Also filed as: LE HUNG · LE HUNG Q · LE HUNG QUI
195 granted patents·18 pending applications·3,260 citations·filing 1994–2023
99Inventor score
Files withIBM192ABERNATHY CHRISTOPHER M4CAIN III HAROLD W3ABERNATHY CHRISTOPHER MICHAEL2HALL RONALD P2
Top patents by PatentIndex Score
213 records- 0198US6631463B1Method and apparatus for patching problematic instructions in a microprocessor using software interruptsIBM·Filed 1999·Granted Oct 7, 2003·417 cites·30 claims
- 0297US9720696B2Independent mapping of threadsIBM·Filed 2014·Granted Aug 1, 2017·30 cites·6 claims
- 0397US8108655B2Selecting fixed-point instructions to issue on load-store unitABERNATHY CHRISTOPHER MICHAEL·Filed 2009·Granted Jan 31, 2012·148 cites·20 claims
- 0496US10037211B2Operation of a multi-slice processor with an expanded merge fetching queueIBM·Filed 2016·Granted Jul 31, 2018·15 cites·17 claims
- 0596US9672043B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2014·Granted Jun 6, 2017·29 cites·8 claims
- 0696US7487334B2Branch encoding before instruction cache writeIBM·Filed 2005·Granted Feb 3, 2009·61 cites·1 claims
- 0796US7269715B2Instruction grouping history on fetch-side dispatch group formationIBM·Filed 2005·Granted Sep 11, 2007·62 cites·14 claims
- 0896US6721874B1Method and system for dynamically shared completion table supporting multiple threads in a processing systemIBM·Filed 2000·Granted Apr 13, 2004·128 cites·23 claims
- 0995US9690586B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2014·Granted Jun 27, 2017·26 cites·4 claims
- 1095US9665372B2Parallel slice processor with dynamic instruction stream mappingIBM·Filed 2014·Granted May 30, 2017·25 cites·16 claims
- 1195US8117403B2Transactional memory system which employs thread assists using address history tablesHELLER JR THOMAS J·Filed 2007·Granted Feb 14, 2012·49 cites·19 claims
- 1295US7877580B2Branch lookahead prefetch for microprocessorsIBM·Filed 2007·Granted Jan 25, 2011·41 cites·9 claims
- 1394US9690585B2Parallel slice processor with dynamic instruction stream mappingIBM·Filed 2014·Granted Jun 27, 2017·22 cites·9 claims
- 1493US10387147B2Managing an issue queue for fused instructions and paired instructions in a microprocessorIBM·Filed 2017·Granted Aug 20, 2019·7 cites·11 claims
- 1593US9870229B2Independent mapping of threadsIBM·Filed 2015·Granted Jan 16, 2018·8 cites·9 claims
- 1693US7904661B2Data stream prefetching in a microprocessorIBM·Filed 2007·Granted Mar 8, 2011·32 cites·13 claims
- 1793US7395414B2Dynamic recalculation of resource vector at issue queue for steering of dependent instructionsIBM·Filed 2005·Granted Jul 1, 2008·31 cites·6 claims
- 1892US9977678B2Reconfigurable parallel execution and load-store slice processorIBM·Filed 2015·Granted May 22, 2018·7 cites·10 claims
- 1992US7467325B2Processor instruction retry recoveryIBM·Filed 2005·Granted Dec 16, 2008·26 cites·12 claims
- 2091US10042770B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2016·Granted Aug 7, 2018·6 cites·7 claims
- 2191US10037229B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2016·Granted Jul 31, 2018·6 cites·13 claims
- 2291US8683175B2Seamless interface for multi-threaded core acceleratorsEKANADHAM KATTAMURI·Filed 2011·Granted Mar 25, 2014·19 cites·20 claims
- 2391US6988186B2Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entryIBM·Filed 2001·Granted Jan 17, 2006·70 cites·12 claims
- 2490US9971602B2Reconfigurable processing method with modes controlling the partitioning of clusters and cache slicesIBM·Filed 2015·Granted May 15, 2018·6 cites·5 claims
- 2590US7350029B2Data stream prefetching in a microprocessorIBM·Filed 2005·Granted Mar 25, 2008·22 cites·7 claims
- 2690US6480931B1Content addressable storage apparatus and register mapper architectureIBM·Filed 1999·Granted Nov 12, 2002·87 cites·35 claims
- 2789US8521998B2Instruction tracking system for processorsABERNATHY CHRISTOPHER MICHAEL·Filed 2010·Granted Aug 27, 2013·12 cites·22 claims
- 2888US9524171B1Split-level history buffer in a computer processing unitIBM·Filed 2016·Granted Dec 20, 2016·4 cites·1 claims
- 2987US7472258B2Dynamically shared group completion table between multiple threadsIBM·Filed 2003·Granted Dec 30, 2008·45 cites·12 claims
- 3087US7254697B2Method and apparatus for dynamic modification of microprocessor instruction group at dispatchIBM·Filed 2005·Granted Aug 7, 2007·18 cites·14 claims
- 3186US10394565B2Managing an issue queue for fused instructions and paired instructions in a microprocessorIBM·Filed 2017·Granted Aug 27, 2019·3 cites·6 claims
- 3286US10223125B2Linkable issue queue parallel execution slice processing methodIBM·Filed 2018·Granted Mar 5, 2019·3 cites·20 claims
- 3386US10083039B2Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slicesIBM·Filed 2018·Granted Sep 25, 2018·3 cites·20 claims
- 3486US10073699B2Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architectureIBM·Filed 2015·Granted Sep 11, 2018·5 cites·20 claims
- 3585US9792147B2Transactional storage accesses supporting differing priority levelsIBM·Filed 2015·Granted Oct 17, 2017·4 cites·16 claims
- 3685US7594096B2Load lookahead prefetch for microprocessorsIBM·Filed 2007·Granted Sep 22, 2009·13 cites·20 claims
- 3784US7827443B2Processor instruction retry recoveryIBM·Filed 2008·Granted Nov 2, 2010·12 cites·19 claims
- 3884US7380066B2Store stream prefetching in a microprocessorIBM·Filed 2005·Granted May 27, 2008·13 cites·7 claims
- 3984US6553480B1System and method for managing the execution of instruction groups having multiple executable instructionsIBM·Filed 1999·Granted Apr 22, 2003·113 cites·27 claims
- 4083US11132198B2Instruction handling for accumulation of register results in a microprocessorIBM·Filed 2019·Granted Sep 28, 2021·2 cites·25 claims
- 4183US11119772B2Check pointing of accumulator register results in a microprocessorIBM·Filed 2019·Granted Sep 14, 2021·3 cites·18 claims
- 4283US9519479B2Techniques for increasing vector processing utilization and efficiency through vector lane predication predictionGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 13, 2016·7 cites·12 claims
- 4383US7631308B2Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessorsIBM·Filed 2005·Granted Dec 8, 2009·12 cites·3 claims
- 4482US10983800B2Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slicesIBM·Filed 2018·Granted Apr 20, 2021·2 cites·20 claims
- 4582US10073697B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2016·Granted Sep 11, 2018·2 cites·5 claims
- 4682US8725993B2Thread transition managementABERNATHY CHRISTOPHER M·Filed 2011·Granted May 13, 2014·4 cites·6 claims
- 4782US7392366B2Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetchesIBM·Filed 2005·Granted Jun 24, 2008·9 cites·26 claims
- 4882US7237094B2Instruction group formation and mechanism for SMT dispatchIBM·Filed 2004·Granted Jun 26, 2007·33 cites·21 claims
- 4981US10157064B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2017·Granted Dec 18, 2018·2 cites·15 claims
- 5081US10133576B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2015·Granted Nov 20, 2018·2 cites·18 claims
Showing the top 50 of 213 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →