Inventor · disambiguated record
Ruben Molina
Also filed as: MOLINA JR RUBEN · MOLINA JR RUBEN SALVADOR · MOLINA RUBEN · MOLINA RUBEN SALVADOR
9 granted patents·87 citations·filing 2001–2012
86Inventor score
Top patents by PatentIndex Score
9 records- 0187US7480881B2Method and computer program for static timing analysis with delay de-rating and clock conservatism reductionLSI LOGIC CORP·Filed 2006·Granted Jan 20, 2009·26 cites·34 claims
- 0276US7062737B2Method of automated repair of crosstalk violations and timing violations in an integrated circuit designLSI LOGIC CORP·Filed 2004·Granted Jun 13, 2006·23 cites·22 claims
- 0371US6810505B2Integrated circuit design flow with capacitive marginLSI LOGIC CORP·Filed 2002·Granted Oct 26, 2004·18 cites·11 claims
- 0468US7739639B2Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layerLSI CORP·Filed 2006·Granted Jun 15, 2010·3 cites·15 claims
- 0562US6442737B1Method of generating an optimal clock buffer set for minimizing clock skew in balanced clock treesLSI LOGIC CORP·Filed 2001·Granted Aug 27, 2002·9 cites·8 claims
- 0661US6948142B2Intelligent engine for protection against injected crosstalk delayLSI LOGIC CORP·Filed 2003·Granted Sep 20, 2005·8 cites·18 claims
- 0753US8775995B2Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layerLSI CORP·Filed 2012·Granted Jul 8, 2014·0 cites·6 claims
- 0843US8321826B2Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layerMOLINA JR RUBEN SALVADOR·Filed 2010·Granted Nov 27, 2012·0 cites·18 claims
- 0938US6835972B2Bowtie and T-shaped structures of L-shaped mesh implementationLSI LOGIC CORP·Filed 2003·Granted Dec 28, 2004·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →