Inventor · disambiguated record
Hsing-Ya Tsao
Also filed as: TSAO HSING-YA
80 granted patents·4 pending applications·3,760 citations·filing 1996–2014
99Inventor score
Files withAPLUS FLASH TECHNOLOGY INC57APLUS INTEGRATED CIRCUITS INC15LEE PETER WUNG8LEE PETER W2ABEDNEJA ASSETS AG L L C1
Top patents by PatentIndex Score
84 records- 0198US9171627B2Non-boosting program inhibit scheme in NAND designAPLUS FLASH TECHNOLOGY INC·Filed 2013·Granted Oct 27, 2015·44 cites·33 claims
- 0298US6862223B1Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2002·Granted Mar 1, 2005·130 cites·28 claims
- 0398US6714457B1Parallel channel programming scheme for MLC flash memoryAPLUS FLASH TECHNOLOGY INC·Filed 2002·Granted Mar 30, 2004·164 cites·36 claims
- 0498US5768193ABit-refreshable method and circuit for refreshing a nonvolatile flash memoryAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Jun 16, 1998·207 cites·19 claims
- 0597US7102929B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Sep 5, 2006·51 cites·5 claims
- 0696US6620682B1Set of three level concurrent word line bias conditions for a nor type flash memory arrayAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Sep 16, 2003·110 cites·8 claims
- 0796US5822252AFlash memory wordline decoder with overerase repairAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Oct 13, 1998·181 cites·28 claims
- 0896US5748538AOR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell arrayAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted May 5, 1998·182 cites·10 claims
- 0995US7110302B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Sep 19, 2006·25 cites·52 claims
- 1095US7075826B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Jul 11, 2006·28 cites·8 claims
- 1195US6850438B2Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operationsAPLUS FLASH TECHNOLOGY INC·Filed 2003·Granted Feb 1, 2005·75 cites·23 claims
- 1295US6556481B13-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cellAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Apr 29, 2003·114 cites·22 claims
- 1395US5978283ACharge pump circuitsAPLUS FLASH TECHNOLOGY INC·Filed 1998·Granted Nov 2, 1999·147 cites·18 claims
- 1494US6757196B1Two transistor flash memory cell for use in EEPROM arrays with a programmable logic deviceAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Jun 29, 2004·83 cites·39 claims
- 1594US5835420ANode-precise voltage regulation for a MOS memory systemAPLUS FLASH TECHNOLOGY INC·Filed 1997·Granted Nov 10, 1998·104 cites·34 claims
- 1694US5748545AMemory device with on-chip manufacturing and memory cell defect detection capabilityAPLUS INTEGRATED CIRCUITS INC·Filed 1997·Granted May 5, 1998·116 cites·40 claims
- 1793US9019764B2Low-voltage page buffer to be used in NVM designAPLUS FLASH TECHNOLOGY INC·Filed 2012·Granted Apr 28, 2015·17 cites·23 claims
- 1893US7324384B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2006·Granted Jan 29, 2008·18 cites·20 claims
- 1993US6498752B1Three step write process used for a nonvolatile NOR type EEPROM memoryAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Dec 24, 2002·83 cites·39 claims
- 2093US6381670B1Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operationAPLUS FLASH TECHNOLOGY INC·Filed 1997·Granted Apr 30, 2002·147 cites·43 claims
- 2192US6788612B2Flash memory array structure suitable for multiple simultaneous operationsAPLUS FLASH TECHNOLOGY INC·Filed 2003·Granted Sep 7, 2004·50 cites·9 claims
- 2292US6023188APositive/negative high voltage charge pump systemAPLUS FLASH TECHNOLOGY INC·Filed 1999·Granted Feb 8, 2000·101 cites·20 claims
- 2392US6009022ANode-precise voltage regulation for a MOS memory systemAPLUS FLASH TECHNOLOGY INC·Filed 1998·Granted Dec 28, 1999·83 cites·20 claims
- 2491US8289775B2Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an arrayLEE PETER WUNG·Filed 2009·Granted Oct 16, 2012·24 cites·77 claims
- 2591US7636252B2Nonvolatile memory with a unified cell structureLEE PETER W·Filed 2006·Granted Dec 22, 2009·17 cites·20 claims
- 2691US7289366B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2006·Granted Oct 30, 2007·19 cites·40 claims
- 2791US7120064B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Oct 10, 2006·15 cites·20 claims
- 2891US5930826AFlash memory protection attribute status bits held in a flash memory arrayAPLUS INTEGRATED CIRCUITS INC·Filed 1997·Granted Jul 27, 1999·94 cites·12 claims
- 2991US5777923AFlash memory read/write controllerAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Jul 7, 1998·79 cites·22 claims
- 3090US8923049B21T1b and 2T2b flash-based, data-oriented EEPROM designAPLUS FLASH TECHNOLOGY INC·Filed 2013·Granted Dec 30, 2014·11 cites·45 claims
- 3190US8072811B2NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory arrayLEE PETER WUNG·Filed 2009·Granted Dec 6, 2011·18 cites·92 claims
- 3290US7283401B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2006·Granted Oct 16, 2007·17 cites·10 claims
- 3390US6660585B1Stacked gate flash memory cell with reduced disturb conditionsAPLUS FLASH TECHNOLOGY INC·Filed 2000·Granted Dec 9, 2003·48 cites·1 claims
- 3490US6031765AReversed split-gate cell arrayAPLUS FLASH TECHNOLOGY INC·Filed 1999·Granted Feb 29, 2000·77 cites·16 claims
- 3589US5978277ABias condition and X-decoder circuit of flash memory arrayAPLUS FLASH TECHNOLOGY INC·Filed 1998·Granted Nov 2, 1999·72 cites·37 claims
- 3688US6628563B1Flash memory array for multiple simultaneous operationsAPLUS FLASH TECHNOLOGY INC·Filed 2002·Granted Sep 30, 2003·48 cites·35 claims
- 3788US5774396AFlash memory with row redundancyAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Jun 30, 1998·71 cites·30 claims
- 3887US7064978B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2003·Granted Jun 20, 2006·33 cites·10 claims
- 3987US5917757AFlash memory with high speed erasing structure using thin oxide semiconductor devicesAPLUS FLASH TECHNOLOGY INC·Filed 1997·Granted Jun 29, 1999·67 cites·40 claims
- 4086US7372736B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2006·Granted May 13, 2008·13 cites·13 claims
- 4185US8634241B2Universal timing waveforms sets to improve random access read and write speed of memoriesLEE PETER WUNG·Filed 2011·Granted Jan 21, 2014·8 cites·6 claims
- 4285US8345481B2NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory arrayAPLUS FLASH TECHNOLOGY INC·Filed 2011·Granted Jan 1, 2013·8 cites·160 claims
- 4385US6818491B2Set of three level concurrent word line bias conditions for a NOR type flash memory arrayAPLUS FLASH TECHNOLOGY INC·Filed 2003·Granted Nov 16, 2004·29 cites·7 claims
- 4485US6584034B1Flash memory array structure suitable for multiple simultaneous operationsAPLUS FLASH TECHNOLOGY INC·Filed 2002·Granted Jun 24, 2003·28 cites·11 claims
- 4585US5687121AFlash EEPROM worldline decoderAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Nov 11, 1997·58 cites·36 claims
- 4684US6275417B1Multiple level flash memoryAPLUS FLASH TECHNOLOGY INC·Filed 2000·Granted Aug 14, 2001·35 cites·15 claims
- 4783US7154783B2Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operationsAPLUS FLASH TECHNOLOGY INC·Filed 2004·Granted Dec 26, 2006·21 cites·3 claims
- 4882US6777292B2Set of three level concurrent word line bias conditions for a NOR type flash memory arrayAPLUS FLASH TECHNOLOGY INC·Filed 2003·Granted Aug 17, 2004·23 cites·9 claims
- 4982US5920503AFlash memory with novel bitline decoder and sourceline latchAPLUS FLASH TECHNOLOGY INC·Filed 1997·Granted Jul 6, 1999·49 cites·20 claims
- 5081US7349257B2Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operationsAPLUS FLASH TECHNOLOGY INC·Filed 2006·Granted Mar 25, 2008·8 cites·4 claims
Showing the top 50 of 84 patent records by PatentIndex Score.
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