Inventor · disambiguated record
Anthony Sanders
Also filed as: SANDERS ANTHONY · SANDERS ANTHONY F · SANDERS ANTHONY FRASER
17 granted patents·6 pending applications·60 citations·filing 2000–2024
91Inventor score
Top patents by PatentIndex Score
23 records- 0176US10069586B2Optical network power consumption mitigationPITZER ARMIN·Filed 2011·Granted Sep 4, 2018·4 cites·13 claims
- 0275US7721130B2Apparatus and method for switching an apparatus to a power saving modeQIMONDA AG·Filed 2006·Granted May 18, 2010·8 cites·33 claims
- 0375US6975141B2LVDS driver for small supply voltagesINFINEON TECHNOLOGIES AG·Filed 2004·Granted Dec 13, 2005·18 cites·8 claims
- 0475US2025062851A1Optical network power consumption mitigationMAXLINEAR INC·Filed 2024·Application pending·0 cites
- 0573US12136998B2Optical network power consumption mitigationMAXLINEAR INC·Filed 2023·Granted Nov 5, 2024·0 cites·20 claims
- 0672US7620136B2Clock and data recovery circuit having gain controlINFINEON TECHNOLOGIES AG·Filed 2006·Granted Nov 17, 2009·5 cites·24 claims
- 0771US11558137B2Optical network power consumption mitigationMAXLINEAR INC·Filed 2018·Granted Jan 17, 2023·1 cites·20 claims
- 0865US11664916B2Optical network power consumption mitigationMAXLINEAR INC·Filed 2020·Granted May 30, 2023·0 cites·20 claims
- 0962US7966469B2Memory system and method for operating a memory systemQIMONDA AG·Filed 2006·Granted Jun 21, 2011·5 cites·29 claims
- 1058US9001952B2Master slave interfaceSANDERS ANTHONY·Filed 2012·Granted Apr 7, 2015·1 cites·21 claims
- 1157US8699647B2Fast phase alignment for clock and data recoveryWENSKE HOLGER·Filed 2009·Granted Apr 15, 2014·5 cites·15 claims
- 1253US8204167B2Master slave interfaceSANDERS ANTHONY·Filed 2008·Granted Jun 19, 2012·1 cites·8 claims
- 1350US6486699B1Compensation circuit for driver circuitsINFINEON TECHNOLOGIES AG·Filed 2000·Granted Nov 26, 2002·7 cites·8 claims
- 1446US7936201B2Apparatus and method for providing a signal for transmission via a signal lineQIMONDA AG·Filed 2006·Granted May 3, 2011·0 cites·28 claims
- 1545US7420430B2Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signalsINFINEON TECHNOLOGIES AG·Filed 2005·Granted Sep 2, 2008·1 cites·19 claims
- 1641US2008123792A1Apparatus and method for transmitting signals over a signal linePRETE EDOARDO·Filed 2006·Application pending·0 cites
- 1739US7532695B2Clock signal extraction device and method for extracting a clock signal from data signalINFINEON TECHNOLOGIES AG·Filed 2002·Granted May 12, 2009·2 cites·20 claims
- 1836US7405591B2Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltageQIMONDA AG·Filed 2006·Granted Jul 29, 2008·0 cites·33 claims
- 1934US7782927B2Generating a transmission clock signal and a reception clock signal for a transceiver using an oscillatorLANTIQ DEUTSCHLAND GMBH·Filed 2004·Granted Aug 24, 2010·2 cites·2 claims
- 2034US2007183552A1Clock and data recovery circuit including first and second stagesSANDERS ANTHONY F·Filed 2006·Application pending·0 cites
- 2134US2007177702A1Receiving data over channels with intersymbol interferenceSANDERS ANTHONY F·Filed 2006·Application pending·0 cites
- 2233US2007288716A1Memory system with a retiming circuit and a method of exchanging data and timing signals between a memory controller and a memory deviceINFINEON TECHNOLOGIES AG·Filed 2006·Application pending·0 cites
- 2332US2008126624A1Memory buffer and method for buffering dataPRETE EDOARDO·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →