Inventor · disambiguated record
Takashi Nasuno
Also filed as: NASUNO TAKASHI
2 granted patents·2 pending applications·13 citations·filing 2003–2006
56Inventor score
Technology areasH10P
Top patents by PatentIndex Score
4 records- 0165US7176486B2Structure of test element group wiring and semiconductor substrateROHM CO LTD·Filed 2004·Granted Feb 13, 2007·10 cites·5 claims
- 0249US7125794B2Method of manufacturing semiconductor deviceRENESAS TECH CORP·Filed 2004·Granted Oct 24, 2006·3 cites·9 claims
- 0345US2006131578A1Structure of semiconductor substrate including test element group wiringROHM CO LTD·Filed 2006·Application pending·0 cites
- 0435US2005181576A1Method for forming inorganic porus filmSEMICONDUCTOR LEADING EDGE TEC·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →