Inventor · disambiguated record
Joseph Roland Verock
Also filed as: VEROCK JOSEPH ROLAND
2 granted patents·15 citations·filing 2000–2000
57Inventor score
Technology areasG06F
Files withIBM2
Top patents by PatentIndex Score
2 records- 0162US6571374B1Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chipsIBM·Filed 2000·Granted May 27, 2003·11 cites·20 claims
- 0250US6567958B1Invention to allow hierarchical logical-to-physical checking on chipsIBM·Filed 2000·Granted May 20, 2003·4 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →