Inventor · disambiguated record
Naichih Chang
Also filed as: CHANG NAICHIH · CHANG NAICHIH NEIL
12 granted patents·4 pending applications·94 citations·filing 2005–2007
90Inventor score
Top patents by PatentIndex Score
16 records- 0193US7738502B2Signal noise filtering in a serial interfaceINTEL CORP·Filed 2006·Granted Jun 15, 2010·35 cites·17 claims
- 0280US7797463B2Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applicationsINTEL CORP·Filed 2005·Granted Sep 14, 2010·9 cites·19 claims
- 0378US7747788B2Hardware oriented target-side native command queuing tag managementINTEL CORP·Filed 2005·Granted Jun 29, 2010·10 cites·19 claims
- 0478US7643410B2Method and apparatus for managing a connection in a connection orientated environmentINTEL CORP·Filed 2006·Granted Jan 5, 2010·9 cites·12 claims
- 0576US7650540B2Detecting and differentiating SATA loopback modesINTEL CORP·Filed 2006·Granted Jan 19, 2010·7 cites·30 claims
- 0668US7805543B2Hardware oriented host-side native command queuing tag managementINTEL CORP·Filed 2005·Granted Sep 28, 2010·4 cites·16 claims
- 0768US7506080B2Parallel processing of frame based data transfersINTER CORP·Filed 2005·Granted Mar 17, 2009·6 cites·16 claims
- 0864US7730239B2Data buffer management in a resource limited environmentINTEL CORP·Filed 2006·Granted Jun 1, 2010·3 cites·18 claims
- 0964US7676604B2Task context direct indexing in a protocol engineINTEL CORP·Filed 2005·Granted Mar 9, 2010·3 cites·13 claims
- 1062US8135869B2Task scheduling to devices with same connection addressCHANG NAICHIH·Filed 2005·Granted Mar 13, 2012·4 cites·11 claims
- 1161US8032675B2Dynamic memory buffer allocation method and systemINTEL CORP·Filed 2005·Granted Oct 4, 2011·2 cites·24 claims
- 1260US7970953B2Serial ATA port addressingINTEL CORP·Filed 2005·Granted Jun 28, 2011·2 cites·23 claims
- 1342US2007005898A1Method, apparatus and system for task context cache replacementHALLECK WILLIAM·Filed 2005·Application pending·0 cites
- 1439US2008183921A1Serial advanced technology attachment (SATA) frame information structure (FIS) processingCHANG NAICHIH·Filed 2007·Application pending·0 cites
- 1532US2007002827A1Automated serial protocol target port transport layer retry mechanismLAU VICTOR·Filed 2005·Application pending·0 cites
- 1632US2007011333A1Automated serial protocol initiator port transport layer retry mechanismLAU VICTOR·Filed 2005·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Naichih Chang files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →