Inventor · disambiguated record
Larry J. Thayer
Also filed as: THAYER LARRY · THAYER LARRY J · THAYER LARRY JAY
31 granted patents·6 pending applications·800 citations·filing 1987–2013
97Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO16THAYER LARRY J9HEWLETT PACKARD CO6SHAW MARK2AVAGO TECHNOLOGIES ENTPR IP SINGAPORE PTE LTD1
Top patents by PatentIndex Score
37 records- 0197US7099994B2RAID memory systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Aug 29, 2006·242 cites·17 claims
- 0296US7656727B2Semiconductor memory device and system providing spare memory locationsHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Feb 2, 2010·56 cites·27 claims
- 0394US7227797B2Hierarchical memory correction system and methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Jun 5, 2007·43 cites·27 claims
- 0487US8634221B2Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a methodTHAYER LARRY J·Filed 2011·Granted Jan 21, 2014·8 cites·25 claims
- 0587US8473791B2Redundant memory to mask DRAM failuresSHAW MARK·Filed 2007·Granted Jun 25, 2013·19 cites·9 claims
- 0687US5278949APolygon renderer which determines the coordinates of polygon edges to sub-pixel resolution in the X,Y and Z coordinates directionsHEWLETT PACKARD CO·Filed 1991·Granted Jan 11, 1994·96 cites·10 claims
- 0787US4965751AGraphics system with programmable tile size and multiplexed pixel data and partial pixel addresses based on tile sizeHEWLETT PACKARD CO·Filed 1987·Granted Oct 23, 1990·99 cites·8 claims
- 0883US7975205B2Error correction algorithm selection based upon memory organizationHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Jul 5, 2011·12 cites·28 claims
- 0982US9298668B2Bit error rate reduction buffer, method and apparatusTHAYER LARRY J·Filed 2010·Granted Mar 29, 2016·5 cites·5 claims
- 1082US7996710B2Defect management for a semiconductor memory systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Aug 9, 2011·13 cites·22 claims
- 1182US5493644APolygon span interpolator with main memory Z bufferHEWLETT PACKARD CO·Filed 1991·Granted Feb 20, 1996·99 cites·17 claims
- 1281US7783935B2Bit error rate reduction bufferHEWLETT PACKARD DEVELOPMENT CO·Filed 2006·Granted Aug 24, 2010·8 cites·4 claims
- 1375US9182925B2Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposerAVAGO TECHNOLOGIES GENERAL IP·Filed 2013·Granted Nov 10, 2015·3 cites·29 claims
- 1474US8554991B2High speed interface for dynamic random access memory (DRAM)THAYER LARRY J·Filed 2011·Granted Oct 8, 2013·5 cites·14 claims
- 1573US8612797B2Systems and methods of selectively managing errors in memory modulesTHAYER LARRY J·Filed 2006·Granted Dec 17, 2013·11 cites·20 claims
- 1673US7307902B2Memory correction system and methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Dec 11, 2007·7 cites·23 claims
- 1769US8914683B2Repairing high-speed serial linksTHAYER LARRY J·Filed 2008·Granted Dec 16, 2014·4 cites·13 claims
- 1869US7539931B2Storage element for mitigating soft errors in logicHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted May 26, 2009·7 cites·14 claims
- 1967US7103826B2Memory system and controller for sameHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 5, 2006·12 cites·16 claims
- 2061US8352896B2System and method for distribution analysis of stacked-die integrated circuitsAVAGO TECHNOLOGIES ENTPR IP SINGAPORE PTE LTD·Filed 2011·Granted Jan 8, 2013·1 cites·15 claims
- 2160US8886892B2Memory module and method employing a multiplexer to replace a memory deviceTHAYER LARRY J·Filed 2007·Granted Nov 11, 2014·4 cites·20 claims
- 2260US7599235B2Memory correction system and methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Oct 6, 2009·3 cites·20 claims
- 2359US8386702B2Memory controllerHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Feb 26, 2013·1 cites·23 claims
- 2457US6943804B2System and method for performing BLTsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 13, 2005·4 cites·22 claims
- 2554US6940525B2Method and apparatus for performing a perspective projection in a graphics device of a computer graphics display systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 6, 2005·4 cites·14 claims
- 2652US6876224B2Method and apparatus for high speed bus having adjustable, symmetrical, edge-rate controlled, waveformsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Apr 5, 2005·5 cites·14 claims
- 2749US7694193B2Systems and methods for implementing a stride value for accessing memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Apr 6, 2010·0 cites·17 claims
- 2847US7844868B2System and method for implementing a stride value for memory testingHEWLETT PACKARD DEVELOPMENT CO·Filed 2010·Granted Nov 30, 2010·0 cites·15 claims
- 2942US2003226090A1System and method for preventing memory access errorsFiled 2002·Application pending·0 cites
- 3042US2006236158A1Memory element for mitigating soft errors in logicTHAYER LARRY J·Filed 2005·Application pending·0 cites
- 3142US2006248355A1Power throttling system and method for a memory controllerTHAYER LARRY J·Filed 2005·Application pending·0 cites
- 3242US2007094569A1Determining hard errors vs. soft errors in memoryTHAYER LARRY J·Filed 2005·Application pending·0 cites
- 3340US6084601ACorner buffer system for improved memory read efficiency during texture mappingHEWLETT PACKARD CO·Filed 1998·Granted Jul 4, 2000·10 cites·4 claims
- 3439US6362824B1System-wide texture offset addressing with page residence indicators for improved performanceHEWLETT PACKARD CO·Filed 1999·Granted Mar 26, 2002·9 cites·26 claims
- 3537US6509905B2Method and apparatus for performing a perspective projection in a graphics device of a computer graphics display systemHEWLETT PACKARD CO·Filed 1998·Granted Jan 21, 2003·10 cites·12 claims
- 3634US2008077840A1Memory system and method for storing and correcting dataSHAW MARK·Filed 2006·Application pending·0 cites
- 3732US2005027932A1Content addressable memory with redundant stored dataFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →