Inventor · disambiguated record
Nien-Yu Tsai
Also filed as: TSAI NIEN-YU
21 granted patents·6 pending applications·294 citations·filing 1998–2024
94Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD13PROMOS TECHNOLOGIES INC8PROMOS TECHNOLOGY INC2TSAI NIEN-YU2
Top patents by PatentIndex Score
27 records- 0196US11106852B2Standard cell and semiconductor device including anchor nodes and method of makingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Aug 31, 2021·3 cites·20 claims
- 0294US6306772B1Deep trench bottle-shaped etching using Cl2 gasPROMOS TECHNOLOGY INC·Filed 2000·Granted Oct 23, 2001·178 cites·20 claims
- 0387US9514266B2Method and system of determining colorability of a layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Dec 6, 2016·9 cites·20 claims
- 0485US10713407B2Standard cell and semiconductor device including anchor nodesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jul 14, 2020·2 cites·20 claims
- 0585US10162928B2Method of designing a semiconductor device, system for implementing the method and standard cellTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Dec 25, 2018·3 cites·20 claims
- 0683US12223251B2Standard cell and semiconductor device including anchor nodesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Feb 11, 2025·0 cites·20 claims
- 0780US10430544B2Multi-patterning graph reduction and checking flow methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Oct 1, 2019·2 cites·20 claims
- 0876US2025054857A1Integrated circuit device and systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0975US11714946B2Standard cell and semiconductor device including anchor nodes and method of makingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Aug 1, 2023·0 cites·20 claims
- 1069US12165969B2Integrated circuit device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Dec 10, 2024·0 cites·20 claims
- 1169US11681850B2Multi-patterning graph reduction and checking flow methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jun 20, 2023·0 cites·20 claims
- 1266US11017148B2Multi-patterning graph reduction and checking flow methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted May 25, 2021·0 cites·20 claims
- 1366US6071823ADeep trench bottle-shaped etch in centura mark II NGPROMOS TECHNOLOGY INC·Filed 1999·Granted Jun 6, 2000·39 cites·16 claims
- 1461US6743726B2Method for etching a trench through an anti-reflective coatingPROMOS TECHNOLOGIES INC·Filed 2002·Granted Jun 1, 2004·10 cites·15 claims
- 1560US9038010B2DRC format for stacked CMOS designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted May 19, 2015·1 cites·16 claims
- 1659US6143653AMethod of forming tungsten interconnect with tungsten oxidation to prevent tungsten lossPROMOS TECHNOLOGIES INC·Filed 1998·Granted Nov 7, 2000·25 cites·12 claims
- 1748US10121694B2Methods of manufacturing a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Nov 6, 2018·0 cites·20 claims
- 1846US6514817B1Method of forming shallow trenchPROMOS TECHNOLOGIES INC·Filed 2002·Granted Feb 4, 2003·3 cites·12 claims
- 1943US6410417B1Method of forming tungsten interconnect and vias without tungsten loss during wet stripping of photoresist polymerPROMOS TECHNOLOGIES INC·Filed 1998·Granted Jun 25, 2002·11 cites·3 claims
- 2041US6998277B2Method of planarizing spin-on material layer and manufacturing photoresist layerPROMOS TECHNOLOGIES INC·Filed 2004·Granted Feb 14, 2006·2 cites·29 claims
- 2140US8895447B2Semiconductor hole structureTSAI NIEN-YU·Filed 2012·Granted Nov 25, 2014·0 cites·13 claims
- 2237US2004067654A1Method of reducing wafer etching defectPROMOS TECHNOLOGIES INC·Filed 2002·Application pending·0 cites
- 2335US6312983B1Etching method for reducing bit line coupling in a DRAMPROMOS TECHNOLOGIES INC·Filed 1999·Granted Nov 6, 2001·6 cites·1 claims
- 2432US2003059996A1Method for forming gate structurePROMOS TECHNOLOGIES INC·Filed 2002·Application pending·0 cites
- 2532US2002142613A1Method for controlling etching depthFiled 2001·Application pending·0 cites
- 2632US2013214424A1Structure and manufacturing method for reducing stress of chipTSAI NIEN-YU·Filed 2012·Application pending·0 cites
- 2724US2002066884A1Etching gas for silicon etch backFiled 1999·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →