Inventor · disambiguated record
Jeff V. Tran
Also filed as: TRAN JEFF V · TRAN JEFF VAN
6 granted patents·1 pending application·97 citations·filing 1999–2011
83Inventor score
Top patents by PatentIndex Score
7 records- 0185US6188247B1Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elementsIBM·Filed 1999·Granted Feb 13, 2001·56 cites·37 claims
- 0273US9021156B2Integrating intellectual property (IP) blocks into a processorNIMMALA PRASHANTH·Filed 2011·Granted Apr 28, 2015·6 cites·19 claims
- 0361US6150869AMethod and apparatus for body control in silicon-on-insulator (SOI) domino circuitsIBM·Filed 1999·Granted Nov 21, 2000·17 cites·16 claims
- 0454US6094072AMethods and apparatus for bipolar elimination in silicon-on-insulator (SOI) domino circuitsIBM·Filed 1999·Granted Jul 25, 2000·15 cites·12 claims
- 0541US6271686B2Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuitsIBM·Filed 2000·Granted Aug 7, 2001·1 cites·22 claims
- 0631US6278157B1Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elementsIBM·Filed 1999·Granted Aug 21, 2001·2 cites·18 claims
- 0729US2002060594A1Method and apparatus for a high frequency, low power clock distribution within a vlsi chipFiled 1999·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →