Inventor · disambiguated record
Nathan P. Chelstrom
Also filed as: CHELSTROM NATHAN · CHELSTROM NATHAN P · CHELSTROM NATHAN PAUL
15 granted patents·3 pending applications·81 citations·filing 2004–2009
92Inventor score
Top patents by PatentIndex Score
18 records- 0188US7484153B2Systems and methods for LBIST testing using isolatable scan chainsTOSHIBA KK·Filed 2005·Granted Jan 27, 2009·17 cites·8 claims
- 0287US7500164B2Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologiesIBM·Filed 2006·Granted Mar 3, 2009·18 cites·1 claims
- 0383US7233188B1Methods and apparatus for reducing power consumption in a processor using clock signal controlSONY COMPUTER ENTERTAINMENT INC·Filed 2005·Granted Jun 19, 2007·13 cites·17 claims
- 0478US7702944B2Dynamic frequency scaling sequence for multi-gigahertz microprocessorsIBM·Filed 2009·Granted Apr 20, 2010·7 cites·5 claims
- 0575US7492793B2Method for controlling asynchronous clock domains to perform synchronous operationsIBM·Filed 2005·Granted Feb 17, 2009·5 cites·1 claims
- 0664US7478300B2Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit deviceIBM·Filed 2006·Granted Jan 13, 2009·4 cites·1 claims
- 0761US7627771B2Clock control hierarchy for integrated microprocessors and systems-on-a-chipIBM·Filed 2005·Granted Dec 1, 2009·2 cites·20 claims
- 0860US7562272B2Apparatus and method for using eFuses to store PLL configuration dataIBM·Filed 2005·Granted Jul 14, 2009·4 cites·1 claims
- 0957US7688930B2Using eFuses to store PLL configuration dataIBM·Filed 2008·Granted Mar 30, 2010·3 cites·14 claims
- 1056US7908536B2Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit deviceIBM·Filed 2008·Granted Mar 15, 2011·2 cites·17 claims
- 1154US7792154B2Controlling asynchronous clock domains to perform synchronous operationsIBM·Filed 2008·Granted Sep 7, 2010·0 cites·1 claims
- 1252US8144689B2Controlling asynchronous clock domains to perform synchronous operationsCHELSTROM NATHAN P·Filed 2008·Granted Mar 27, 2012·1 cites·17 claims
- 1352US7797600B2Method and apparatus for testing a ring of non-scan latches with logic built-in self-testIBM·Filed 2008·Granted Sep 14, 2010·1 cites·14 claims
- 1452US7406640B2Method and apparatus for testing a ring of non-scan latches with logic built-in self-testIBM·Filed 2006·Granted Jul 29, 2008·1 cites·6 claims
- 1550US7516350B2Dynamic frequency scaling sequence for multi-gigahertz microprocessorsIBM·Filed 2004·Granted Apr 7, 2009·3 cites·4 claims
- 1643US2007174679A1Method and apparatus for processing error information and injecting errors in a processor systemIBM·Filed 2006·Application pending·0 cites
- 1736US2007168809A1Systems and methods for LBIST testing using commonly controlled LBIST satellitesKIRYU NAOKI·Filed 2005·Application pending·0 cites
- 1835US2007092048A1RUNN counter phase controlCHELSTROM NATHAN P·Filed 2005·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Nathan P. Chelstrom files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →