Inventor · disambiguated record
Saad Monasa
Also filed as: MONASA SAAD · MONASA SAAD P
7 granted patents·3 pending applications·25 citations·filing 2002–2021
80Inventor score
Top patents by PatentIndex Score
10 records- 0159US7707378B2DDR flash implementation with hybrid row buffers and direct access interface to legacy flash functionsINTEL CORP·Filed 2006·Granted Apr 27, 2010·4 cites·18 claims
- 0257US7034732B1Multi-stage digital-to-analog converterINTEL CORP·Filed 2004·Granted Apr 25, 2006·8 cites·16 claims
- 0353US7551489B2Multi-level memory cell sensingINTEL CORP·Filed 2005·Granted Jun 23, 2009·3 cites·7 claims
- 0452US7265698B2Multi-stage digital-to-analog converterINTEL CORP·Filed 2006·Granted Sep 4, 2007·2 cites·22 claims
- 0552US6707749B2Enabling an interim density for top boot flash memoriesINTEL CORP·Filed 2002·Granted Mar 16, 2004·8 cites·20 claims
- 0651US12249372B2Encoding additional states in a three-dimensional crosspoint memory architectureINTEL CORP·Filed 2021·Granted Mar 11, 2025·0 cites·25 claims
- 0738US8006029B2DDR flash implementation with direct register access to legacy flash functionsINTEL CORP·Filed 2006·Granted Aug 23, 2011·0 cites·15 claims
- 0837US2012191898A1Ddr flash implementation with direct register access to legacy flash functionsGANESAN RAMKARTHIK·Filed 2011·Application pending·0 cites
- 0932US2008133820A1DDR flash implementation with row buffer interface to legacy flash functionsGANESAN RAMKARTHIK·Filed 2006·Application pending·0 cites
- 1031US2005285631A1Data latch pre-equalizationINTEL CORP·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →