Inventor · disambiguated record
Fedor G. Pikus
Also filed as: PIKUS FEDOR · PIKUS FEDOR G
24 granted patents·23 pending applications·122 citations·filing 2004–2020
94Inventor score
Top patents by PatentIndex Score
47 records- 0186US10846448B1Limited basis quantum particle definitions in applications of quantum computing to electronic design automation processesMENTOR GRAPHICS CORP·Filed 2019·Granted Nov 24, 2020·9 cites·20 claims
- 0286US9652581B2Directed self-assembly-aware layout decomposition for multiple patterningMENTOR GRAPHICS CORP·Filed 2015·Granted May 16, 2017·5 cites·20 claims
- 0384US10895864B2Fabric-independent multi-patterningMENTOR GRAPHICS CORP·Filed 2019·Granted Jan 19, 2021·2 cites·20 claims
- 0484US8302039B2Secure exchange of information in electronic design automationFERGUSON JOHN G·Filed 2010·Granted Oct 30, 2012·7 cites·12 claims
- 0584US7698664B2Secure exchange of information in electronic design automationFERGUSON JOHN G·Filed 2007·Granted Apr 13, 2010·10 cites·17 claims
- 0683US8612919B2Model-based design verificationPIKUS FEDOR G·Filed 2007·Granted Dec 17, 2013·14 cites·16 claims
- 0782US10596219B2Logic-driven layout verificationSRINIVASAN SRIDHAR·Filed 2011·Granted Mar 24, 2020·3 cites·14 claims
- 0881US8504949B2Hybrid hotspot detectionROBLES JUAN ANDRES TORRES·Filed 2011·Granted Aug 6, 2013·11 cites·17 claims
- 0978US7222312B2Secure exchange of information in electronic design automationFERGUSON JOHN G·Filed 2004·Granted May 22, 2007·21 cites·13 claims
- 1077US7353468B2Secure exchange of information in electronic design automationFERGUSON JOHN G·Filed 2004·Granted Apr 1, 2008·21 cites·18 claims
- 1173US9729317B2Optical physical uncloneable functionMENTOR GRAPHICS CORP·Filed 2014·Granted Aug 8, 2017·3 cites·18 claims
- 1272US10872191B1Invariant property-based clustering of circuit images for electronic design automation (EDA) applicationsMENTOR GRAPHICS CORP·Filed 2020·Granted Dec 22, 2020·1 cites·20 claims
- 1367US8225246B2Logic injectionPIKUS FEDOR G·Filed 2010·Granted Jul 17, 2012·2 cites·46 claims
- 1465US7716611B2Logic injectionMENTOR GRAPHICS CORP·Filed 2004·Granted May 11, 2010·10 cites·28 claims
- 1564US11275884B2Systems and methods for photolithographic designSIEMENS IND SOFTWARE INC·Filed 2020·Granted Mar 15, 2022·0 cites·9 claims
- 1664US10311197B2Preserving hierarchy and coloring uniformity in multi-patterning layout designMENTOR GRAPHICS CORP·Filed 2016·Granted Jun 4, 2019·1 cites·20 claims
- 1762US9652574B2Simultaneous multi-layer fill generationANIKIN EUGENE·Filed 2011·Granted May 16, 2017·2 cites·8 claims
- 1859US10789408B2Systems and methods for photolithographic designMENTOR GRAPHICS CORP·Filed 2018·Granted Sep 29, 2020·0 cites·20 claims
- 1954US10552565B2Simultaneous multi-layer fill generationMENTOR GRAPHICS CORP·Filed 2016·Granted Feb 4, 2020·0 cites·20 claims
- 2053US10908511B2Systems and methods for patterning color assignmentMENTOR GRAPHICS CORP·Filed 2018·Granted Feb 2, 2021·0 cites·20 claims
- 2153US2014337810A1Modular platform for integrated circuit design analysis and verificationMENTOR GRAPHICS CORP·Filed 2013·Application pending·0 cites
- 2252US2017220729A1Directed Self-Assembly-Aware Layout Decomposition For Multiple PatterningMENTOR GRAPHICS CORP·Filed 2017·Application pending·0 cites
- 2351US2008148348A1Secure exchange of information in electronic design automationFERGUSON JOHN G·Filed 2008·Application pending·0 cites
- 2450US2010185995A1Electrostatic Damage Protection Circuitry VerificationPIKUS FEDOR G·Filed 2009·Application pending·0 cites
- 2549US9940428B2Hierarchical fill in a design layoutMENTOR GRAPHICS CORP·Filed 2014·Granted Apr 10, 2018·0 cites·18 claims
- 2649US8751981B2Logic injectionPIKUS FEDOR G·Filed 2012·Granted Jun 10, 2014·0 cites·20 claims
- 2747US2010229133A1Property-Based Classification In Electronic Design AutomationPIKUS FEDOR G·Filed 2009·Application pending·0 cites
- 2847US2009106715A1Programmable Design Rule CheckingPIKUS FEDOR·Filed 2008·Application pending·0 cites
- 2947US2009319579A1Electronic Design Automation Process RestartPIKUS FEDOR·Filed 2008·Application pending·0 cites
- 3047US2010023897A1Property-Based Classification In Electronic Design AutomationPIKUS FEDOR G·Filed 2009·Application pending·0 cites
- 3145US2009077506A1Simultaneous Multi-Layer Fill GenerationANIKIN EUGENE·Filed 2008·Application pending·0 cites
- 3245US2013080985A1Electrostatic damage protection circuitry verificationPIKUS FEDOR G·Filed 2012·Application pending·0 cites
- 3345US2011145772A1Modular Platform For Integrated Circuit Design Analysis And VerificationPIKUS FEDOR G·Filed 2010·Application pending·0 cites
- 3444US10210302B2Electrostatic damage protection circuitry verificationMENTOR GRAPHICS CORP·Filed 2016·Granted Feb 19, 2019·0 cites·20 claims
- 3544US2010023905A1Critical Area Deterministic SamplingPIKUS FEDOR G·Filed 2009·Application pending·0 cites
- 3643US2021150001A1Adaptive penalty term determinations in applications of quantum computing to electronic design automation processesMENTOR GRAPHICS CORP·Filed 2019·Application pending·0 cites
- 3743US2007256046A1Analysis and optimization of manufacturing yield improvementsMENTOR GRAPHICS CORP·Filed 2006·Application pending·0 cites
- 3843US2007055892A1Concealment of information in electronic design automationMENTOR GRAPHICS CORP·Filed 2006·Application pending·0 cites
- 3943US2009222927A1Concealment of Information in Electronic Design AutomationPIKUS FEDOR G·Filed 2007·Application pending·0 cites
- 4042US2009235213A1Layout-Versus-Schematic Analysis For Symmetric CircuitsHAO XIN·Filed 2008·Application pending·0 cites
- 4142US2008034332A1Optimization Of Geometry Pattern DensityMENTOR GRAPHICS CORP·Filed 2007·Application pending·0 cites
- 4241US2010185994A1Topological Pattern MatchingPIKUS FEDOR G·Filed 2009·Application pending·0 cites
- 4341US2006259978A1Secure exchange of information in electronic design automation with license-related key generationPIKUS FEDOR G·Filed 2006·Application pending·0 cites
- 4439US10643015B2Properties in electronic design automationPIKUS FEDOR G·Filed 2007·Granted May 5, 2020·0 cites·19 claims
- 4537US2013198703A1Virtual Flat Traversal Of A Hierarchical Circuit DesignLU ZIYANG·Filed 2012·Application pending·0 cites
- 4637US2012198394A1Method For Improving Circuit Design RobustnessPIKUS FEDOR G·Filed 2011·Application pending·0 cites
- 4736US2011145770A1Device AnnotationBROOKS PHILLIP A·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →