Inventor · disambiguated record
Richard E. Matick
Also filed as: MATICK RICHARD E · MATICK RICHARD EDWARD
27 granted patents·2 pending applications·1,079 citations·filing 1976–2008
97Inventor score
Files withIBM29
Top patents by PatentIndex Score
29 records- 0197US4577293ADistributed, on-chip cacheIBM·Filed 1984·Granted Mar 18, 1986·145 cites·9 claims
- 0295US4541075ARandom access memory having a second input/output portIBM·Filed 1982·Granted Sep 10, 1985·79 cites·9 claims
- 0394US4649516ADynamic row buffer circuit for DRAMIBM·Filed 1984·Granted Mar 10, 1987·76 cites·14 claims
- 0492US5895487AIntegrated processing and L2 DRAM cacheIBM·Filed 1996·Granted Apr 20, 1999·203 cites·11 claims
- 0592US4667305ACircuits for accessing a variable width data bus with a variable width data fieldIBM·Filed 1982·Granted May 19, 1987·132 cites·5 claims
- 0690US7499312B2Fast, stable, SRAM cell using seven devices and hierarchical bit/sense lineIBM·Filed 2007·Granted Mar 3, 2009·25 cites·4 claims
- 0787US4084230AHybrid semiconductor memory with on-chip associative page addressing, page replacement and controlIBM·Filed 1976·Granted Apr 11, 1978·59 cites·36 claims
- 0885US4287575AHigh speed high density, multi-port random access memory cellIBM·Filed 1979·Granted Sep 1, 1981·30 cites·5 claims
- 0984US4905188AFunctional cache memory chip architecture for improved cache accessIBM·Filed 1988·Granted Feb 27, 1990·85 cites·17 claims
- 1082US7289369B2DRAM hierarchical data pathIBM·Filed 2005·Granted Oct 30, 2007·12 cites·19 claims
- 1181US7133971B2Cache with selective least frequently used or most frequently used cache line replacementIBM·Filed 2003·Granted Nov 7, 2006·21 cites·20 claims
- 1277US7958311B2Cache line replacement techniques allowing choice of LFU or MFU cache line replacementIBM·Filed 2008·Granted Jun 7, 2011·4 cites·18 claims
- 1375US7460387B2eDRAM hierarchical differential sense ampIBM·Filed 2007·Granted Dec 2, 2008·8 cites·8 claims
- 1473US7821858B2eDRAM hierarchical differential sense AMPIBM·Filed 2008·Granted Oct 26, 2010·7 cites·3 claims
- 1573US4589092AData buffer having separate lock bit storage arrayIBM·Filed 1983·Granted May 13, 1986·38 cites·7 claims
- 1671US5388072ABit line switch array for electronic computer memoryIBM·Filed 1992·Granted Feb 7, 1995·32 cites·7 claims
- 1771US4616310ACommunicating random access memoryIBM·Filed 1983·Granted Oct 7, 1986·37 cites·7 claims
- 1869US7471546B2Hierarchical six-transistor SRAMIBM·Filed 2007·Granted Dec 30, 2008·7 cites·6 claims
- 1968US4663729ADisplay architecture having variable data widthIBM·Filed 1984·Granted May 5, 1987·22 cites·9 claims
- 2054US7870341B2Cache line replacement techniques allowing choice of LFU or MFU cache line replacementIBM·Filed 2008·Granted Jan 11, 2011·0 cites·4 claims
- 2154US6081872ACache reloading performance improvement through the use of early select techniques with and without pipeliningIBM·Filed 1997·Granted Jun 27, 2000·28 cites·28 claims
- 2253US7460423B2Hierarchical 2T-DRAM with self-timed sensingIBM·Filed 2007·Granted Dec 2, 2008·2 cites·4 claims
- 2351US7398357B1Cache line replacement techniques allowing choice of LFU or MFU cache line replacementIBM·Filed 2006·Granted Jul 8, 2008·0 cites·8 claims
- 2448US7709299B2Hierarchical 2T-DRAM with self-timed sensingIBM·Filed 2008·Granted May 4, 2010·1 cites·3 claims
- 2548US6981096B1Mapping and logic for combining L1 and L2 directories and/or arraysIBM·Filed 1998·Granted Dec 27, 2005·21 cites·8 claims
- 2646US2008270683A1Systems and methods for a dram concurrent refresh engine with processor interfaceIBM·Filed 2007·Application pending·0 cites
- 2740US2008016277A1Dram hierarchical data pathIBM·Filed 2007·Application pending·0 cites
- 2836US5870108AInformation handling system including mapping of graphics display data to a video buffer for fast updation of graphic primitivesIBM·Filed 1997·Granted Feb 9, 1999·5 cites·6 claims
- 2930US5890215AElectronic computer memory system having multiple width, high speed communication bufferIBM·Filed 1994·Granted Mar 30, 1999·0 cites·16 claims
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