Inventor · disambiguated record
Donald J. O'Riordan
Also filed as: O'RIORDAN DONALD · O'RIORDAN DONALD J · O'RIORDAN DONALD JOHN
44 granted patents·1 pending application·744 citations·filing 1999–2014
98Inventor score
Files withCADENCE DESIGN SYSTEMS INC25O'RIORDAN DONALD J10MAJUMDER CHAYAN4GINETTI ARNOLD2CHETPUT CHANDRASHEKAR L1
Top patents by PatentIndex Score
45 records- 0195US9182948B1Method and system for navigating hierarchical levels using graphical previewsO'RIORDAN DONALD J·Filed 2010·Granted Nov 10, 2015·38 cites·27 claims
- 0295US8683400B1System and method for fault sensitivity analysis of mixed-signal integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Mar 25, 2014·24 cites·17 claims
- 0395US7917877B2System and method for circuit schematic generationCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Mar 29, 2011·199 cites·24 claims
- 0493US8762906B2Method, system, and computer program product for implementing multi-power domain digital / mixed signal verification and low power simulationGINETTI ARNOLD·Filed 2010·Granted Jun 24, 2014·23 cites·29 claims
- 0593US8732636B2Method, system, and computer program product for implementing multi-power domain digital / mixed-signal verification and low power simulationGINETTI ARNOLD·Filed 2010·Granted May 20, 2014·23 cites·26 claims
- 0691US9009635B1System and method for simulator assertion synthesis and digital equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Apr 14, 2015·13 cites·20 claims
- 0791US7865857B1System and method for improved visualization and debugging of constraint circuit objectsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jan 4, 2011·48 cites·33 claims
- 0891US7367006B1Hierarchical, rules-based, general property visualization and editing method and systemCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Apr 29, 2008·32 cites·43 claims
- 0990US7735036B2System and method enabling circuit topology recognition with auto-interactive constraint application and smart checkingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jun 8, 2010·32 cites·26 claims
- 1089US8689121B2System and method for management of controls in a graphical user interfaceO'RIORDAN DONALD J·Filed 2010·Granted Apr 1, 2014·14 cites·34 claims
- 1189US8554530B1Methods and systems for property assertion in circuit simulationO'RIORDAN DONALD·Filed 2009·Granted Oct 8, 2013·37 cites·39 claims
- 1288US9032347B1System and method for automated simulator assertion synthesis and digital equivalence checkingCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 12, 2015·9 cites·16 claims
- 1388US9026963B1System and method for fault sensitivity analysis of mixed-signal integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted May 5, 2015·7 cites·19 claims
- 1488US8949203B1Verification of design libraries and databasesO'RIORDAN DONALD J·Filed 2012·Granted Feb 3, 2015·15 cites·18 claims
- 1588US8838559B1Data mining through property checks based upon string pattern determinationsO'RIORDAN DONALD J·Filed 2011·Granted Sep 16, 2014·12 cites·23 claims
- 1687US8875077B1Fault sensitivity analysis-based cell-aware automated test pattern generation flowCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Oct 28, 2014·16 cites·20 claims
- 1785US9047424B1System and method for analog verification IP authoring and storageCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jun 2, 2015·8 cites·23 claims
- 1885US8234617B2Method and system for re-using digital assertions in a mixed signal designCHETPUT CHANDRASHEKAR L·Filed 2009·Granted Jul 31, 2012·16 cites·30 claims
- 1983US9589085B1Systems and methods for viewing analog simulation check violations in an electronic design automation frameworkCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 7, 2017·8 cites·20 claims
- 2082US9355130B1Method and system for component parameter managementO'RIORDAN DONALD J·Filed 2012·Granted May 31, 2016·7 cites·25 claims
- 2182US8832612B1Netlisting analog/mixed-signal schematics to VAMSCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Sep 9, 2014·6 cites·5 claims
- 2281US8813004B1Analog fault visualization system and method for circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Aug 19, 2014·7 cites·20 claims
- 2381US8601412B1Netlisting analog/mixed-signal schematics to VAMSO'RIORDAN DONALD J·Filed 2011·Granted Dec 3, 2013·6 cites·20 claims
- 2481US8214791B1User interface for inherited connections in a circuitO'RIORDAN DONALD J·Filed 2009·Granted Jul 3, 2012·10 cites·20 claims
- 2580US10445290B1System and method for a smart configurable high performance interactive log file viewerCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Oct 15, 2019·8 cites·20 claims
- 2679US9213787B1Simulation based system and method for gate oxide reliability enhancementCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 15, 2015·5 cites·20 claims
- 2778US9245088B1System and method for data mining safe operating area violationsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jan 26, 2016·4 cites·20 claims
- 2876US9501598B1System and method for assertion publication and re-useCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Nov 22, 2016·4 cites·17 claims
- 2976US8863050B1Efficient single-run method to determine analog fault coverage versus bridge resistanceCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Oct 14, 2014·6 cites·32 claims
- 3074US8954307B1Chained programming language preprocessors for circuit simulationO'RIORDAN DONALD J·Filed 2011·Granted Feb 10, 2015·4 cites·21 claims
- 3173US10133653B2Recording and playback of trace and video log data for programsORIORDAN DONALD J·Filed 2012·Granted Nov 20, 2018·6 cites·18 claims
- 3273US8176463B2Modeling and simulating device mismatch for designing integrated circuitsO'RIORDAN DONALD J·Filed 2009·Granted May 8, 2012·8 cites·26 claims
- 3369US8438531B2Visualization and information display for shapes in displayed graphical imagesMAJUMDER CHAYAN·Filed 2009·Granted May 7, 2013·5 cites·31 claims
- 3469US7085700B2Method for debugging of analog and mixed-signal behavioral models during simulationCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Aug 1, 2006·20 cites·26 claims
- 3568US8296717B1Method and system for implementing inherited connections for electronics designsO'RIORDAN DONALD J·Filed 2010·Granted Oct 23, 2012·2 cites·30 claims
- 3668US6381563B1System and method for simulating circuits using inline subcircuitsCADENCE DESIGN SYSTEMS INC·Filed 1999·Granted Apr 30, 2002·52 cites·47 claims
- 3767US9038008B1System and method for containing analog verification IPCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted May 19, 2015·2 cites·20 claims
- 3865US8711177B1Generation, display, and manipulation of measurements in computer graphical designsMAJUMDER CHAYAN·Filed 2011·Granted Apr 29, 2014·2 cites·33 claims
- 3964US8645901B2Visualization and information display for shapes in displayed graphical images based on a cursorMAJUMDER CHAYAN·Filed 2009·Granted Feb 4, 2014·3 cites·20 claims
- 4061US9020277B1Image-based stimulus for circuit simulationCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Apr 28, 2015·1 cites·21 claims
- 4160US8533626B2Visualization and information display for shapes in displayed graphical images based on user zone of focusMAJUMDER CHAYAN·Filed 2009·Granted Sep 10, 2013·2 cites·21 claims
- 4249US2010287493A1Method and system for viewing and editing an image in a magnified viewCADENCE DESIGN SYSTEMS INC·Filed 2009·Application pending·0 cites
- 4345US10223484B1Spice model bin inheritance mechanismCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 5, 2019·0 cites·20 claims
- 4442US8996348B1System and method for fault sensitivity analysis of digitally-calibrated-circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Mar 31, 2015·0 cites·20 claims
- 4542US8200915B2Management of very large streaming data sets for efficient writes and reads to and from persistent storagePICHUMANI RAMANI·Filed 2008·Granted Jun 12, 2012·0 cites·31 claims
Join the waitlist — get patent alerts
Get an alert when Donald J. O'Riordan files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →