Inventor · disambiguated record
Edward A. Brekelbaum
Also filed as: BREKELBAUM EDWARD · BREKELBAUM EDWARD A
14 granted patents·2 pending applications·143 citations·filing 2002–2017
92Inventor score
Top patents by PatentIndex Score
16 records- 0194US7692946B2Memory array on more than one dieINTEL CORP·Filed 2007·Granted Apr 6, 2010·40 cites·22 claims
- 0291US10540287B2Spatial memory streaming confidence mechanismSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Jan 21, 2020·8 cites·17 claims
- 0383US10417130B2System and method for spatial memory streaming trainingSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Sep 17, 2019·3 cites·24 claims
- 0476US7130990B2Efficient instruction scheduling with lossy tracking of scheduling informationINTEL CORP·Filed 2002·Granted Oct 31, 2006·22 cites·20 claims
- 0574US7313676B2Register renaming for dynamic multi-threadingINTEL CORP·Filed 2002·Granted Dec 25, 2007·21 cites·30 claims
- 0670US7228402B2Predicate register file write by an instruction with a pending instruction having data dependencyINTEL CORP·Filed 2002·Granted Jun 5, 2007·15 cites·20 claims
- 0765US8059441B2Memory array on more than one dieTAUFIQUE MOHAMMED H·Filed 2010·Granted Nov 15, 2011·2 cites·22 claims
- 0863US7111154B2Method and apparatus for NOP foldingINTEL CORP·Filed 2003·Granted Sep 19, 2006·9 cites·21 claims
- 0961US7428631B2Apparatus and method using different size rename registers for partial-bit and bulk-bit writesINTEL CORP·Filed 2003·Granted Sep 23, 2008·8 cites·14 claims
- 1060US7418551B2Multi-purpose register cacheINTEL CORP·Filed 2004·Granted Aug 26, 2008·7 cites·25 claims
- 1153US6954848B2Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediatelyINTEL CORP·Filed 2002·Granted Oct 11, 2005·3 cites·24 claims
- 1251US7171545B2Predictive filtering of register cache entryINTEL CORP·Filed 2003·Granted Jan 30, 2007·2 cites·24 claims
- 1347US10387320B2Integrated confirmation queuesSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Aug 20, 2019·0 cites·20 claims
- 1447US9977674B2Micro-operation generator for deriving a plurality of single-destination micro-operations from a given predicated instructionRUPLEY II JEFFREY P·Filed 2003·Granted May 22, 2018·3 cites·47 claims
- 1540US2004064679A1Hierarchical scheduling windowsFiled 2003·Application pending·0 cites
- 1640US2004064678A1Hierarchical scheduling windowsFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →