Inventor · disambiguated record
Warren R. Morrow
Also filed as: MORROW WARREN · MORROW WARREN R
22 granted patents·4 pending applications·406 citations·filing 1994–2024
96Inventor score
Top patents by PatentIndex Score
26 records- 0195US7366368B2Optical add/drop interconnect bus for multiprocessor architectureINTEL CORP·Filed 2004·Granted Apr 29, 2008·59 cites·13 claims
- 0287US7318130B2System and method for thermal throttling of memory modulesINTEL CORP·Filed 2004·Granted Jan 8, 2008·59 cites·24 claims
- 0386US8135999B2Disabling outbound drivers for a last memory buffer on a memory channelMORROW WARREN·Filed 2010·Granted Mar 13, 2012·7 cites·4 claims
- 0486US7386768B2Memory channel with bit lane fail-overINTEL CORP·Filed 2003·Granted Jun 10, 2008·29 cites·4 claims
- 0586US2024379625A1Stacked memory with interface providing offset interconnectsTAHOE RES LTD·Filed 2024·Application pending·0 cites
- 0685US7130229B2Interleaved mirrored memory systemsINTEL CORP·Filed 2002·Granted Oct 31, 2006·40 cites·26 claims
- 0781US6693450B1Dynamic swing voltage adjustmentINTEL CORP·Filed 2000·Granted Feb 17, 2004·24 cites·16 claims
- 0879US8489944B2Disabling outbound drivers for a last memory buffer on a memory channelMORROW WARREN·Filed 2012·Granted Jul 16, 2013·4 cites·15 claims
- 0979US8020056B2Memory channel with bit lane fail-overINTEL CORP·Filed 2010·Granted Sep 13, 2011·4 cites·11 claims
- 1077US7761753B2Memory channel with bit lane fail-overINTEL CORP·Filed 2008·Granted Jul 20, 2010·4 cites·19 claims
- 1175US7076618B2Memory controllers with interleaved mirrored memory modesINTEL CORP·Filed 2005·Granted Jul 11, 2006·8 cites·13 claims
- 1274US6487627B1Method and apparatus to manage digital bus trafficINTEL CORP·Filed 1999·Granted Nov 26, 2002·64 cites·15 claims
- 1372US7017017B2Memory controllers with interleaved mirrored memory modesINTEL CORP·Filed 2002·Granted Mar 21, 2006·15 cites·24 claims
- 1469US8510612B2Disabling outbound drivers for a last memory buffer on a memory channelVOGT PETE D·Filed 2012·Granted Aug 13, 2013·1 cites·9 claims
- 1565US6708240B1Managing resources in a bus bridgeINTEL CORP·Filed 2000·Granted Mar 16, 2004·11 cites·29 claims
- 1664US8971087B2Stacked memory with interface providing offset interconnectsVOGT PETE·Filed 2011·Granted Mar 3, 2015·1 cites·21 claims
- 1763US12046577B2Stacked memory with interface providing offset interconnectsTAHOE RES LTD·Filed 2019·Granted Jul 23, 2024·0 cites·20 claims
- 1862US5721857AMethod and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessorINTEL CORP·Filed 1996·Granted Feb 24, 1998·41 cites·19 claims
- 1959US9768148B2Stacked memory with interface providing offset interconnectsINTEL CORP·Filed 2014·Granted Sep 19, 2017·0 cites·24 claims
- 2057US2018122779A1STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect SINTEL CORP·Filed 2017·Application pending·0 cites
- 2155US7269481B2Method and apparatus for memory bandwidth thermal budgettingINTEL CORP·Filed 2003·Granted Sep 11, 2007·4 cites·24 claims
- 2254US8286039B2Disabling outbound drivers for a last memory buffer on a memory channelVOGT PETE D·Filed 2011·Granted Oct 9, 2012·0 cites·4 claims
- 2345US5612909AMethod and apparatus for rounding operands using previous rounding historyINTEL CORP·Filed 1994·Granted Mar 18, 1997·15 cites·29 claims
- 2441US6502154B1Bus bridging method and apparatus including use of read size indicatorsINTEL CORP·Filed 1999·Granted Dec 31, 2002·16 cites·23 claims
- 2540US2005147414A1Low latency optical memory busFiled 2003·Application pending·0 cites
- 2633US2014089755A1Reliability enhancements for high speed memory - parity protection on command/address and ecc protection on dataKANTAMSETTI SHVETA·Filed 2012·Application pending·0 cites
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