Inventor · disambiguated record
Stephen Keith Heinrich-Barna
Also filed as: HEINRICH-BARNA STEPHEN · HEINRICH-BARNA STEPHEN K · HEINRICH-BARNA STEPHEN KEITH
17 granted patents·2 pending applications·54 citations·filing 2001–2023
91Inventor score
Top patents by PatentIndex Score
19 records- 0194US9401196B1Dual mode ferroelectric random access memory (FRAM) cell apparatus and methods with imprinted read-only (RO) dataTEXAS INSTRUMENTS INC·Filed 2015·Granted Jul 26, 2016·13 cites·5 claims
- 0282US7379354B2Methods and apparatus to provide voltage control for SRAM write assist circuitsTEXAS INSTRUMENTS INC·Filed 2006·Granted May 27, 2008·16 cites·26 claims
- 0377US10535409B2Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbsTEXAS INSTRUMENTS INC·Filed 2016·Granted Jan 14, 2020·4 cites·25 claims
- 0477US9799408B2Memory circuit with leakage compensationTEXAS INSTRUMENTS INC·Filed 2016·Granted Oct 24, 2017·4 cites·2 claims
- 0577US9202859B1Well resistors and polysilicon resistorsTEXAS INSTRUMENTS INC·Filed 2014·Granted Dec 1, 2015·3 cites·10 claims
- 0675US10504567B2Sense amplifier with offset compensationTEXAS INSTRUMENTS INC·Filed 2019·Granted Dec 10, 2019·3 cites·19 claims
- 0760US10062443B2Memory circuit with leakage compensationTEXAS INSTRUMENTS INC·Filed 2017·Granted Aug 28, 2018·1 cites·4 claims
- 0859US12494906B2Systems and methods for implementing structures for physical unclonable functionsANAMETRIC INC·Filed 2023·Granted Dec 9, 2025·0 cites·19 claims
- 0958US6646925B2Method and system for discharging the bit lines of a memory cell array after erase operationTEXAS INSTRUMENTS INC·Filed 2001·Granted Nov 11, 2003·10 cites·13 claims
- 1057US11670386B2Method for suppressing gate oxide tunnel current in non-volatile memory to reduce disturbsTEXAS INSTRUMENTS INC·Filed 2020·Granted Jun 6, 2023·0 cites·16 claims
- 1152US9379176B2Well resistors and polysilicon resistorsTEXAS INSTRUMENTS INC·Filed 2015·Granted Jun 28, 2016·0 cites·10 claims
- 1250US9711715B2Method of manufacturing a dual mode ferroelectric random access memory (FRAM) having imprinted read-only (RO) dataTEXAS INSTRUMENTS INC·Filed 2016·Granted Jul 18, 2017·0 cites·9 claims
- 1348US10593413B2Memory circuit with leakage compensationTEXAS INSTRUMENTS INC·Filed 2018·Granted Mar 17, 2020·0 cites·4 claims
- 1443US10199078B2Sense amplifier with offset compensationTEXAS INSTRUMENTS INC·Filed 2017·Granted Feb 5, 2019·0 cites·11 claims
- 1541US9704554B2Sense amplifier with offset compensationTEXAS INSTRUMENTS INC·Filed 2015·Granted Jul 11, 2017·0 cites·20 claims
- 1640US7813198B2System and method for reading memoryTEXAS INSTRUMENTS INC·Filed 2008·Granted Oct 12, 2010·0 cites·21 claims
- 1739US9236107B1FRAM cell with cross point accessTEXAS INSTRUMENTS INC·Filed 2014·Granted Jan 12, 2016·0 cites·6 claims
- 1833US2007081379A1Write assist for latch and memory circuitsTEXAS INSTRUMENTS INC·Filed 2005·Application pending·0 cites
- 1929US2003095439A1Method and system for minimizing bit stress in a non-volatile memory during erase operationsTEXAS INSTRUMENTS INC·Filed 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →