Inventor · disambiguated record
Regis Colwell
Also filed as: COLWELL REGIS · COLWELL REGIS R
16 granted patents·268 citations·filing 2003–2021
93Inventor score
Top patents by PatentIndex Score
16 records- 0197US7543262B2Analog layout module generator and methodCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Jun 2, 2009·138 cites·24 claims
- 0295US10699051B1Method and system for performing cross-validation for model-based layout recommendationsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jun 30, 2020·32 cites·20 claims
- 0395US10628546B1Method and system for automatically extracting layout design patterns for custom layout design reuse through interactive recommendationsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Apr 21, 2020·28 cites·20 claims
- 0490US8806405B2Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Aug 12, 2014·22 cites·41 claims
- 0586US9064063B1Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraintsYU HENRY·Filed 2012·Granted Jun 23, 2015·13 cites·31 claims
- 0685US11087060B1System, method, and computer program product for the integration of machine learning predictors in an automatic placement associated with an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Aug 10, 2021·6 cites·17 claims
- 0785US10949596B1System, method, and computer program product for simultaneous routing and placement in an electronic circuit designCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 16, 2021·2 cites·15 claims
- 0883US9990461B1Method and apparatus for placement and routing of analog componentsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jun 5, 2018·5 cites·20 claims
- 0979US10747936B1System, method, and computer program product for genetic routing in an electronic circuit designCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Aug 18, 2020·2 cites·20 claims
- 1074US11275882B1System, method, and computer program product for group and isolation prediction using machine learning and applications in analog placement and sizingCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Mar 15, 2022·2 cites·20 claims
- 1174US11263381B1System and method for updating shapes associated with an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Mar 1, 2022·1 cites·20 claims
- 1274US8694943B1Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awarenessYU HENRY·Filed 2012·Granted Apr 8, 2014·4 cites·42 claims
- 1370US12045730B1System, method, and computer program product for analog and mix-signal circuit placementCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jul 23, 2024·1 cites·16 claims
- 1466US7945890B2Registry for electronic design automation of integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 17, 2011·4 cites·21 claims
- 1559US6918102B2Method and apparatus for exact relative positioning of devices in a semiconductor circuit layoutCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jul 12, 2005·7 cites·22 claims
- 1655US9202000B1Implementing designs of guard ring and fill structures from simple unit cellsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 1, 2015·1 cites·19 claims
Join the waitlist — get patent alerts
Get an alert when Regis Colwell files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →