Inventor · disambiguated record
Paul G. Filseth
Also filed as: FILSETH PAUL · FILSETH PAUL G
17 granted patents·1 pending application·202 citations·filing 1991–2012
94Inventor score
Top patents by PatentIndex Score
18 records- 0191US6768958B2Automatic calibration of a masking process simulatorLSI LOGIC CORP·Filed 2002·Granted Jul 27, 2004·35 cites·28 claims
- 0283US6611953B1Mask correction optimizationLSI LOGIC CORP·Filed 2001·Granted Aug 26, 2003·23 cites·26 claims
- 0382US6782525B2Wafer process critical dimension, alignment, and registration analysis simulation toolLSI LOGIC CORP·Filed 2002·Granted Aug 24, 2004·23 cites·20 claims
- 0481US8023644B2Multimode block cipher architecturesLSI CORP·Filed 2007·Granted Sep 20, 2011·10 cites·1 claims
- 0578US8359479B2High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacksLSI CORP·Filed 2008·Granted Jan 22, 2013·9 cites·25 claims
- 0670US6934410B1Mask correction for photolithographic processesLSI LOGIC CORP·Filed 2001·Granted Aug 23, 2005·13 cites·28 claims
- 0767US6868355B2Automatic calibration of a masking process simulatorLSI LOGIC CORP·Filed 2004·Granted Mar 15, 2005·7 cites·30 claims
- 0866US7961872B2Flexible hardware architecture for ECC/HECC based cryptographyLSI CORP·Filed 2007·Granted Jun 14, 2011·4 cites·1 claims
- 0965US8411853B2Alternate galois field advanced encryption standard roundFILSETH PAUL G·Filed 2008·Granted Apr 2, 2013·4 cites·20 claims
- 1065US7171047B2Adaptive Sem edge recognition algorithmLSI LOGIC CORP·Filed 2002·Granted Jan 30, 2007·11 cites·15 claims
- 1163US8015540B2Method and system for reducing inter-layer capacitance in integrated circuitsLSI CORP·Filed 2008·Granted Sep 6, 2011·2 cites·6 claims
- 1262US5473546AMethod for flattening hierarchical design descriptionsLSI LOGIC CORP·Filed 1991·Granted Dec 5, 1995·37 cites·6 claims
- 1358US7149340B2Mask defect analysis for both horizontal and vertical processing effectsLSI LOGIC CORP·Filed 2002·Granted Dec 12, 2006·12 cites·26 claims
- 1457US7264906B2OPC based illumination optimization with mask error constraintsLSI CORP·Filed 2004·Granted Sep 4, 2007·4 cites·9 claims
- 1555US6701511B1Optical and etch proximity correctionLSI LOGIC CORP·Filed 2001·Granted Mar 2, 2004·4 cites·4 claims
- 1652US7396760B2Method and system for reducing inter-layer capacitance in integrated circuitsLSI CORP·Filed 2004·Granted Jul 8, 2008·4 cites·19 claims
- 1740US8898539B2Correcting errors in miscorrected codewords using list decodingHAN YANG·Filed 2012·Granted Nov 25, 2014·0 cites·17 claims
- 1837US2011255689A1Multiple-mode cryptographic module usable with memory controllersLSI CORP·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →