Inventor · disambiguated record
Reynante Tamunan Alvarado
Also filed as: ALVARADO REYNANTE · ALVARADO REYNANTE T · ALVARADO REYNANTE TAMUNAN
18 granted patents·4 pending applications·113 citations·filing 2000–2020
93Inventor score
Technology areasH10W
Top patents by PatentIndex Score
22 records- 0191US8686560B2Wafer-level chip-scale package device having bump assemblies configured to mitigate failures due to stressPARVARANDEH PIROOZ·Filed 2010·Granted Apr 1, 2014·15 cites·9 claims
- 0290US7973418B2Solder bump interconnect for improved mechanical and thermo-mechanical performanceFLIPCHIP INT LLC·Filed 2008·Granted Jul 5, 2011·27 cites·20 claims
- 0387US8188606B2Solder bump interconnectALVARADO REYNANTE·Filed 2011·Granted May 29, 2012·12 cites·20 claims
- 0483US8278748B2Wafer-level packaged device having self-assembled resilient leadsLO CHIUNG C·Filed 2010·Granted Oct 2, 2012·6 cites·41 claims
- 0582US9985010B2System, apparatus, and method for embedding a device in a faceup workpieceQUALCOMM INC·Filed 2015·Granted May 29, 2018·4 cites·18 claims
- 0682US9159684B1Wafer-level packaged device having self-assembled resilient leadsMAXIM INTEGRATED PRODUCTS·Filed 2014·Granted Oct 13, 2015·4 cites·20 claims
- 0780US9171782B2Stacked redistribution layers on dieQUALCOMM INC·Filed 2013·Granted Oct 27, 2015·6 cites·32 claims
- 0880US8692367B1Wafer-level packaged device having self-assembled resilient leadsMAXIM INTEGRATED PRODUCTS·Filed 2012·Granted Apr 8, 2014·4 cites·7 claims
- 0979US9379065B2Crack stopping structure in wafer level packaging (WLP)QUALCOMM INC·Filed 2013·Granted Jun 28, 2016·5 cites·24 claims
- 1078US10163687B2System, apparatus, and method for embedding a 3D component with an interconnect structureQUALCOMM INC·Filed 2015·Granted Dec 25, 2018·3 cites·10 claims
- 1172US9425160B1Wafer-level package device with solder bump reinforcementMAXIM INTEGRATED PRODUCTS·Filed 2013·Granted Aug 23, 2016·3 cites·10 claims
- 1271US8446019B2Solder bump interconnectALVARADO REYNANTE·Filed 2012·Granted May 21, 2013·3 cites·16 claims
- 1368US9209110B2Integrated device comprising wires as vias in an encapsulation layerQUALCOMM INC·Filed 2014·Granted Dec 8, 2015·2 cites·27 claims
- 1466US10141202B2Semiconductor device comprising mold for top side and sidewall protectionQUALCOMM INC·Filed 2013·Granted Nov 27, 2018·2 cites·21 claims
- 1566US6455922B1Deformation-absorbing leadframe for semiconductor devicesTEXAS INSTRUMENTS INC·Filed 2000·Granted Sep 24, 2002·16 cites·10 claims
- 1664US9806052B2Semiconductor package interconnectQUALCOMM INC·Filed 2015·Granted Oct 31, 2017·1 cites·24 claims
- 1745US11545411B2Package comprising wire bonds configured as a heat spreaderQUALCOMM INC·Filed 2020·Granted Jan 3, 2023·0 cites·30 claims
- 1843US2015228594A1Via under the interconnect structures for semiconductor devicesQUALCOMM INC·Filed 2014·Application pending·0 cites
- 1940US9806048B2Planar fan-out wafer level packagingQUALCOMM INC·Filed 2016·Granted Oct 31, 2017·0 cites·23 claims
- 2032US2017373032A1Redistribution layer (rdl) fan-out wafer level packaging (fowlp) structureQUALCOMM INC·Filed 2016·Application pending·0 cites
- 2130US2002190358A1Deformation-absorbing leadframe for semiconductor devicesFiled 2002·Application pending·0 cites
- 2230US2016343646A1High aspect ratio interconnect for wafer level package (wlp) and integrated circuit (ic) packageQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →