Inventor · disambiguated record
Sailendra Chadalavda
Also filed as: CHADALAVDA SAILENDRA
4 granted patents·14 citations·filing 2016–2016
73Inventor score
Files withNVIDIA CORP4
Top patents by PatentIndex Score
4 records- 0189US10281524B2Test partition external input/output interface control for test partitions in a semiconductorNVIDIA CORP·Filed 2016·Granted May 7, 2019·6 cites·12 claims
- 0287US10317463B2Scan system interface (SSI) moduleNVIDIA CORP·Filed 2016·Granted Jun 11, 2019·6 cites·18 claims
- 0378US10444280B2Independent test partition clock coordination across multiple test partitionsNVIDIA CORP·Filed 2016·Granted Oct 15, 2019·2 cites·20 claims
- 0455US10451676B2Method and system for dynamic standard test access (DSTA) for a logic block reuseNVIDIA CORP·Filed 2016·Granted Oct 22, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →