Inventor · disambiguated record
Sudip K. Nag
Also filed as: NAG SUDIP · NAG SUDIP K
33 granted patents·1,127 citations·filing 1993–2014
98Inventor score
Top patents by PatentIndex Score
33 records- 0198US7428722B2Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemesCSWITCH CORP·Filed 2008·Granted Sep 23, 2008·58 cites·8 claims
- 0296US6789244B1Placement of clock objects under constraintsXILINX INC·Filed 2002·Granted Sep 7, 2004·178 cites·20 claims
- 0395US7358761B1Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemesCSITCH CORP·Filed 2005·Granted Apr 15, 2008·59 cites·23 claims
- 0494US6086631APost-placement residual overlap removal method for core-based PLD programming processXILINX INC·Filed 1998·Granted Jul 11, 2000·242 cites·20 claims
- 0593US7143380B1Method for application of network flow techniques under constraintsXILINX INC·Filed 2002·Granted Nov 28, 2006·97 cites·44 claims
- 0689US6021423AMethod for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computationsXILINX INC·Filed 1997·Granted Feb 1, 2000·159 cites·3 claims
- 0779US6766504B1Interconnect routing using logic levelsXILINX INC·Filed 2002·Granted Jul 20, 2004·26 cites·22 claims
- 0878US7605605B2Programmable logic cells with local connectionsCSWITCH CORP·Filed 2005·Granted Oct 20, 2009·9 cites·12 claims
- 0973US6099583ACore-based placement and annealing methods for programmable logic devicesXILINX INC·Filed 1998·Granted Aug 8, 2000·68 cites·20 claims
- 1072US6732349B1Method and apparatus for improving PIP coverage in programmable logic devicesXILINX INC·Filed 2002·Granted May 4, 2004·18 cites·9 claims
- 1171US8448122B1Implementing sub-circuits with predictable behavior within a circuit designSUTHAR VISHAL·Filed 2009·Granted May 21, 2013·7 cites·18 claims
- 1270US6857115B1Placement of objects with partial shape restrictionXILINX INC·Filed 2002·Granted Feb 15, 2005·15 cites·26 claims
- 1368US7072815B1Relocation of components for post-placement optimizationXILINX INC·Filed 2002·Granted Jul 4, 2006·14 cites·24 claims
- 1467US7725868B1Method and apparatus for facilitating signal routing within a programmable logic deviceXILINX INC·Filed 2007·Granted May 25, 2010·3 cites·2 claims
- 1566US7143378B1Method and apparatus for timing characterization of integrated circuit designsXILINX INC·Filed 2003·Granted Nov 28, 2006·11 cites·20 claims
- 1666US7051312B1Upper-bound calculation for placed circuit design performanceXILINX INC·Filed 2003·Granted May 23, 2006·11 cites·34 claims
- 1765US6484298B1Method and apparatus for automatic timing-driven implementation of a circuit designXILINX INC·Filed 2000·Granted Nov 19, 2002·11 cites·20 claims
- 1863US6507860B1System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAsXILINX INC·Filed 2000·Granted Jan 14, 2003·6 cites·2 claims
- 1963US6415425B1Method for analytical placement of cells using density surface representationsXILINX INC·Filed 1999·Granted Jul 2, 2002·38 cites·14 claims
- 2062US9405871B1Determination of path delays in circuit designsXILINX INC·Filed 2014·Granted Aug 2, 2016·1 cites·20 claims
- 2162US7306977B1Method and apparatus for facilitating signal routing within a programmable logic deviceXILINX INC·Filed 2003·Granted Dec 11, 2007·7 cites·12 claims
- 2261US6625795B1Method and apparatus for placement of input-output design objects into a programmable gate arrayXILINX INC·Filed 2001·Granted Sep 23, 2003·9 cites·10 claims
- 2360US6877040B1Method and apparatus for testing routabilityXILINX INC·Filed 2000·Granted Apr 5, 2005·9 cites·21 claims
- 2459US7398496B1Unified placer infrastructureXILINX INC·Filed 2005·Granted Jul 8, 2008·2 cites·9 claims
- 2558US7076758B1Using router feedback for placement improvements for logic designXILINX INC·Filed 2003·Granted Jul 11, 2006·6 cites·22 claims
- 2658US6317768B1System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAsXILINX INC·Filed 2000·Granted Nov 13, 2001·4 cites·4 claims
- 2757US6983439B1Unified placer infrastructureXILINX INC·Filed 2002·Granted Jan 3, 2006·5 cites·8 claims
- 2856US6711600B1System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAsXILINX INC·Filed 2000·Granted Mar 23, 2004·3 cites·2 claims
- 2952US5598343AMethod of segmenting an FPGA channel architecture for maximum routability and performanceTEXAS INSTRUMENTS INC·Filed 1993·Granted Jan 28, 1997·24 cites·1 claims
- 3051US7240315B1Automated local clock placement for FPGA designsXILINX INC·Filed 2003·Granted Jul 3, 2007·4 cites·17 claims
- 3149US7728623B2Programmable logic cells with local connectionsAGATE LOGIC INC·Filed 2006·Granted Jun 1, 2010·1 cites·16 claims
- 3243US6289496B1Placement of input-output design objects into a programmable gate array supporting multiple voltage standardsXILINX INC·Filed 1998·Granted Sep 11, 2001·17 cites·15 claims
- 3336US6167416ASystem and method for RAM-partitioning to exploit parallelism of radix-2 elements in FPGASXILINX INC·Filed 1998·Granted Dec 26, 2000·5 cites·2 claims
Join the waitlist — get patent alerts
Get an alert when Sudip K. Nag files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →