Inventor · disambiguated record
Richard F. Rizzolo
Also filed as: RIZZOLO RICHARD · RIZZOLO RICHARD F · RIZZOLO RICHARD FRANK
18 granted patents·370 citations·filing 1986–2020
94Inventor score
Top patents by PatentIndex Score
18 records- 0188US6490702B1Scan structure for improving transition fault coverage and scan diagnosticsIBM·Filed 1999·Granted Dec 3, 2002·72 cites·11 claims
- 0285US6971054B2Method and system for determining repeatable yield detractors of integrated circuitsIBM·Filed 2002·Granted Nov 29, 2005·36 cites·37 claims
- 0383US6442720B1Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysisIBM·Filed 1999·Granted Aug 27, 2002·50 cites·14 claims
- 0483US5142167AEncoding for simultaneous switching output noise reductionIBM·Filed 1991·Granted Aug 25, 1992·41 cites·19 claims
- 0578US6728914B2Random path delay testing methodologyCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Apr 27, 2004·22 cites·16 claims
- 0678US6662324B1Global transition scan based AC methodIBM·Filed 2000·Granted Dec 9, 2003·22 cites·15 claims
- 0777US9874917B2Adaptive power capping in a chipIBM·Filed 2016·Granted Jan 23, 2018·2 cites·20 claims
- 0869US5455931AProgrammable clock tuning system and methodIBM·Filed 1993·Granted Oct 3, 1995·54 cites·32 claims
- 0967US9733685B2Temperature-aware microprocessor voltage managementIBM·Filed 2015·Granted Aug 15, 2017·1 cites·15 claims
- 1066US6532571B1Method to improve a testability analysis of a hierarchical designIBM·Filed 2000·Granted Mar 11, 2003·15 cites·14 claims
- 1166US6453436B1Method and apparatus for improving transition fault testability of semiconductor chipsIBM·Filed 1999·Granted Sep 17, 2002·26 cites·18 claims
- 1265US9575529B2Voltage droop reduction in a processorIBM·Filed 2015·Granted Feb 21, 2017·1 cites·17 claims
- 1360US11105853B1Empirical LBIST latch switching and state probability determinationIBM·Filed 2020·Granted Aug 31, 2021·0 cites·19 claims
- 1458US6751765B1Method and system for determining repeatable yield detractors of integrated circuitsIBM·Filed 2000·Granted Jun 15, 2004·10 cites·10 claims
- 1555US10048734B2Adaptive power capping in a chipIBM·Filed 2017·Granted Aug 14, 2018·0 cites·1 claims
- 1649US4760289ATwo-level differential cascode current switch mastersliceIBM·Filed 1986·Granted Jul 26, 1988·18 cites·3 claims
- 1747US11501047B2Error injection for timing margin protection and frequency closureIBM·Filed 2019·Granted Nov 15, 2022·0 cites·20 claims
- 1845US7650535B2Array delete mechanisms for shipping a microprocessor with defective arraysIBM·Filed 2006·Granted Jan 19, 2010·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →