Inventor · disambiguated record
Jiun-Ren Lai
Also filed as: LAI JIUN REN
12 granted patents·4 pending applications·410 citations·filing 2001–2024
90Inventor score
Files withMACRONIX INT CO LTD7TAIWAN SEMICONDUCTOR MFG CO LTD4HU HSIEN-PIN1TAIWAN SEMICONDUCTOR MFG1
Top patents by PatentIndex Score
16 records- 0197US12266612B2Method for forming a semiconductor device including forming a first interconnect structure on one side of a substrate having first metal feature closer the substrate than second metal feature and forming first and second tsv on other side of substrate connecting to the metal featuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Apr 1, 2025·2 cites·20 claims
- 0297US6734107B2Pitch reduction in semiconductor fabricationMACRONIX INT CO LTD·Filed 2002·Granted May 11, 2004·322 cites·15 claims
- 0393US11854990B2Method for forming a semiconductor device having TSV formed through a silicon interposer and a second silicon substrate with cavity covering a second dieTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Dec 26, 2023·2 cites·20 claims
- 0490US10297550B23D IC architecture with interposer and interconnect structure for bonding diesHU HSIEN PIN·Filed 2010·Granted May 21, 2019·10 cites·20 claims
- 0588US6548385B1Method for reducing pitch between conductive features, and structure formed using the methodFiled 2002·Granted Apr 15, 2003·53 cites·20 claims
- 0686US2024387393A1Method for Forming a Semiconductor Device Having TSV Formed Through a Silicon Interposer and a Second Silicon Substrate with Cavity Covering a Second DieTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0765US6518103B1Method for fabricating NROM with ONO structureMACRONIX INT CO LTD·Filed 2001·Granted Feb 11, 2003·11 cites·20 claims
- 0863US10923431B2Method for forming a 3D IC architecture including forming a first die on a first side of a first interconnect structure and a second die in an opening formed in a second sideTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Feb 16, 2021·0 cites·20 claims
- 0957US6849526B2Method of improving device resistanceMACRONIX INT CO LTD·Filed 2004·Granted Feb 1, 2005·6 cites·19 claims
- 1048US6492214B2Method of fabricating an insulating layerMACRONIX INT CO LTD·Filed 2002·Granted Dec 10, 2002·3 cites·12 claims
- 1139US6720629B2Structure of a memory device with buried bit lineMACRONIX INT CO LTD·Filed 2002·Granted Apr 13, 2004·1 cites·15 claims
- 1238US2011193235A13DIC Architecture with Die Inside InterposerTAIWAN SEMICONDUCTOR MFG·Filed 2010·Application pending·0 cites
- 1336US6787408B2Method for forming an electrical insulating layer on bit lines of the flash memoryMACRONIX INT CO LTD·Filed 2001·Granted Sep 7, 2004·0 cites·20 claims
- 1435US6537917B2Method for fabricating electrically insulating layersMACRONIX INT CO LTD·Filed 2001·Granted Mar 25, 2003·0 cites·12 claims
- 1533US2005020043A1Methods for reducing cell pitch in semiconductor devicesFiled 2003·Application pending·0 cites
- 1633US2002168834A1Method for fabricating shallow rench isolation structureFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →