Inventor · disambiguated record
Bruce Whitefield
Also filed as: WHITEFIELD BRUCE · WHITEFIELD BRUCE J · WHITEFIELD BRUCE JOSEPH
32 granted patents·4 pending applications·362 citations·filing 1991–2022
97Inventor score
Top patents by PatentIndex Score
36 records- 0194US6936920B2Voltage contrast monitor for integrated circuit defectsLSI LOGIC CORP·Filed 2003·Granted Aug 30, 2005·65 cites·4 claims
- 0291US7460211B2Apparatus for wafer patterning to reduce edge exclusion zoneLSI CORP·Filed 2006·Granted Dec 2, 2008·16 cites·8 claims
- 0388US6495312B1Method and apparatus for removing photoresist edge beads from thin film substratesLSI LOGIC CORP·Filed 2001·Granted Dec 17, 2002·30 cites·11 claims
- 0478US6943042B2Method of detecting spatially correlated variations in a parameter of an integrated circuit dieLSI LOGIC CORP·Filed 2003·Granted Sep 13, 2005·19 cites·7 claims
- 0577US6614507B2Apparatus for removing photoresist edge beads from thin film substratesLSI LOGIC CORP·Filed 2002·Granted Sep 2, 2003·14 cites·16 claims
- 0676US7062415B2Parametric outlier detectionLSI LOGIC CORP·Filed 2004·Granted Jun 13, 2006·22 cites·20 claims
- 0776US6787379B1Method of detecting spatially correlated variations in a parameter of an integrated circuit dieLSI LOGIC CORP·Filed 2001·Granted Sep 7, 2004·17 cites·3 claims
- 0875US6512985B1Process control systemLSI LOGIC CORP·Filed 2000·Granted Jan 28, 2003·24 cites·20 claims
- 0972US7598127B2Nanotube fuse structureNANTERO INC·Filed 2005·Granted Oct 6, 2009·5 cites·3 claims
- 1072US7074710B2Method of wafer patterning for reducing edge exclusion zoneLSI LOGIC CORP·Filed 2004·Granted Jul 11, 2006·12 cites·9 claims
- 1172US6650958B1Integrated process tool monitoring system for semiconductor fabricationLSI LOGIC CORP·Filed 2002·Granted Nov 18, 2003·20 cites·13 claims
- 1269US6767692B1Process for inhibiting edge peeling of coating on semiconductor substrate during formation of integrated circuit structure thereonLSI LOGIC CORP·Filed 2001·Granted Jul 27, 2004·11 cites·12 claims
- 1369US6645857B1Key hole fillingLSI LOGIC CORP·Filed 2002·Granted Nov 11, 2003·17 cites·20 claims
- 1466US7039556B2Substrate profile analysisLSI LOGIC CORP·Filed 2004·Granted May 2, 2006·12 cites·18 claims
- 1566US7013192B2Substrate contact analysisLSI LOGIC CORP·Filed 2004·Granted Mar 14, 2006·6 cites·20 claims
- 1665US7560292B2Voltage contrast monitor for integrated circuit defectsLSI LOGIC CORP·Filed 2007·Granted Jul 14, 2009·1 cites·2 claims
- 1765US7312880B2Wafer edge structure measurement methodLSI CORP·Filed 2004·Granted Dec 25, 2007·7 cites·12 claims
- 1861US7183181B2Dynamic edge bead removalLSI LOGIC CORP·Filed 2004·Granted Feb 27, 2007·8 cites·21 claims
- 1957US8899599B2Clamping mechanism for a two wheel panel dollyWHITEFIELD BRUCE JOSEPH·Filed 2012·Granted Dec 2, 2014·4 cites·12 claims
- 2055US7799166B2Wafer edge expose alignment methodLSI CORP·Filed 2004·Granted Sep 21, 2010·4 cites·6 claims
- 2154US2006069659A1Defect monitoring systemGATOV MICHAEL S·Filed 2004·Application pending·0 cites
- 2252US2022354717A1Assisted rotation deviceCamas Robotics Booster Club·Filed 2022·Application pending·0 cites
- 2351US7323768B2Voltage contrast monitor for integrated circuit defectsLSI LOGIC CORP·Filed 2005·Granted Jan 29, 2008·0 cites·3 claims
- 2450US6971944B2Method and control system for improving CMP process by detecting and reacting to harmonic oscillationLSI LOGIC CORP·Filed 2004·Granted Dec 6, 2005·3 cites·22 claims
- 2549US7930655B2Yield profile manipulatorLSI CORP·Filed 2008·Granted Apr 19, 2011·0 cites·8 claims
- 2649US6986112B2Method of mapping logic failures in an integrated circuit dieLSI LOGIC CORP·Filed 2003·Granted Jan 10, 2006·4 cites·20 claims
- 2748US7137098B2Pattern component analysis and manipulationLSI LOGIC CORP·Filed 2004·Granted Nov 14, 2006·3 cites·20 claims
- 2848US5477466AMethod and structure for improving patterning design for processingLSI LOGIC CORP·Filed 1994·Granted Dec 19, 1995·13 cites·18 claims
- 2948US5379233AMethod and structure for improving patterning design for processingLSI LOGIC CORP·Filed 1991·Granted Jan 3, 1995·13 cites·13 claims
- 3045US5654897AMethod and structure for improving patterning design for processingLSI LOGIC CORP·Filed 1995·Granted Aug 5, 1997·10 cites·29 claims
- 3143US7395522B2Yield profile manipulatorLSI CORP·Filed 2004·Granted Jul 1, 2008·0 cites·12 claims
- 3241US7315360B2Surface coordinate systemLSI LOGIC CORP·Filed 2004·Granted Jan 1, 2008·2 cites·20 claims
- 3340US2006065985A1Substrate edge scribeBERMAN MICHAEL J·Filed 2004·Application pending·0 cites
- 3438US7653523B2Method for calculating high-resolution wafer parameter profilesLSI CORP·Filed 2003·Granted Jan 26, 2010·0 cites·21 claims
- 3537US2006076036A1Metal removal from solventWHITEFIELD BRUCE J·Filed 2004·Application pending·0 cites
- 3633US7277813B2Pattern detection for integrated circuit substratesLSI CORP·Filed 2005·Granted Oct 2, 2007·0 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Bruce Whitefield files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →