Inventor · disambiguated record
Juan Pablo Saenz Echeverry
Also filed as: ECHEVERRY JUAN PABLO SAENZ
9 granted patents·85 citations·filing 2012–2015
88Inventor score
Technology areasG11C
Files withKAMALANATHAN DEEPAK3ADESTO TECHNOLOGIES CORP2ADESTO TECH CORP1DINH JOHN1ECHEVERRY JUAN PABLO SAENZ1
Top patents by PatentIndex Score
9 records- 0195US9165644B2Method of operating a resistive memory device with a ramp-up/ramp-down program/erase pulseKAMALANATHAN DEEPAK·Filed 2012·Granted Oct 20, 2015·31 cites·24 claims
- 0285US9029829B1Resistive switching memoriesECHEVERRY JUAN PABLO SAENZ·Filed 2012·Granted May 12, 2015·14 cites·26 claims
- 0383US9025396B1Pre-conditioning circuits and methods for programmable impedance elements in memory devicesADESTO TECHNOLOGIES CORP·Filed 2013·Granted May 5, 2015·8 cites·28 claims
- 0483US8730752B1Circuits and methods for placing programmable impedance memory elements in high impedance statesKAMALANATHAN DEEPAK·Filed 2012·Granted May 20, 2014·8 cites·23 claims
- 0581US9734902B2Resistive memory device with ramp-up/ramp-down program/erase pulseADESTO TECH CORP·Filed 2015·Granted Aug 15, 2017·5 cites·16 claims
- 0681US9047948B1Programmable window of operation for CBRAMDINH JOHN·Filed 2012·Granted Jun 2, 2015·10 cites·18 claims
- 0775US9007808B1Safeguarding data through an SMT processADESTO TECHNOLOGIES CORP·Filed 2012·Granted Apr 14, 2015·5 cites·20 claims
- 0863US8659954B1CBRAM/ReRAM with improved program and erase algorithmsLEWIS DERRIC·Filed 2012·Granted Feb 25, 2014·4 cites·20 claims
- 0945US9368198B1Circuits and methods for placing programmable impedance memory elements in high impedance statesKAMALANATHAN DEEPAK·Filed 2014·Granted Jun 14, 2016·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →