Inventor · disambiguated record
Leonid Dubrovin
Also filed as: DUBROVIN LEONID
21 granted patents·12 pending applications·31 citations·filing 2009–2012
91Inventor score
Top patents by PatentIndex Score
33 records- 0183US8806137B2Cache replacement using active cache line countersRABINOVITCH ALEXANDER·Filed 2011·Granted Aug 12, 2014·8 cites·21 claims
- 0283US8583874B2Method and apparatus for caching prefetched dataDUBROVIN LEONID·Filed 2010·Granted Nov 12, 2013·9 cites·22 claims
- 0378US9530387B2Adjusting direct memory access transfers used in video decodingAMITAY AMICHAY·Filed 2012·Granted Dec 27, 2016·3 cites·20 claims
- 0472US8880815B2Low access time indirect memory accessesALEXANDRON NIMROD·Filed 2012·Granted Nov 4, 2014·4 cites·20 claims
- 0566US8850123B2Cache prefetch learningDUBROVIN LEONID·Filed 2010·Granted Sep 30, 2014·3 cites·20 claims
- 0662US8661169B2Copying data to a cache using direct memory accessRABINOVITCH ALEXANDER·Filed 2010·Granted Feb 25, 2014·1 cites·18 claims
- 0762US8171269B2Branch target buffer with entry source field for use in determining replacement priorityRABINOVITCH ALEXANDER·Filed 2009·Granted May 1, 2012·2 cites·20 claims
- 0855US8095700B2Controller and method for statistical allocation of multichannel direct memory access bandwidthALEXANDRON NIMROD·Filed 2009·Granted Jan 10, 2012·1 cites·18 claims
- 0950US8527689B2Multi-destination direct memory access transferAMITAY AMICHAY·Filed 2010·Granted Sep 3, 2013·0 cites·20 claims
- 1047US8656107B2On-demand allocation of cache memory for use as a preset bufferRABINOVITCH ALEXANDER·Filed 2012·Granted Feb 18, 2014·0 cites·21 claims
- 1146US9066068B2Intra-prediction mode selection while encoding a pictureRABINOVITCH ALEXANDER·Filed 2011·Granted Jun 23, 2015·0 cites·16 claims
- 1246US8898433B2Efficient extraction of execution sets from fetch setsRABINOVITCH ALEXANDER·Filed 2012·Granted Nov 25, 2014·0 cites·20 claims
- 1345US8898214B2Method and apparatus to perform floating point operationsDUBROVIN LEONID·Filed 2012·Granted Nov 25, 2014·0 cites·21 claims
- 1445US8897355B2Cache prefetch during motion estimationAMITAY AMICHAY·Filed 2011·Granted Nov 25, 2014·0 cites·20 claims
- 1545US8892621B2Implementation of negation in a multiplication operation without post-incrementationDUBROVIN LEONID·Filed 2011·Granted Nov 18, 2014·0 cites·20 claims
- 1644US8891351B2Orthogonal variable spreading factor code sequence generationDUBROVIN LEONID·Filed 2011·Granted Nov 18, 2014·0 cites·20 claims
- 1743US8332546B2Fully asynchronous direct memory access controller and processor workDUBROVIN LEONID·Filed 2010·Granted Dec 11, 2012·0 cites·18 claims
- 1841US8607033B2Sequentially packing mask selected bits from plural words in circularly coupled register pair for transferring filled register bits to memoryALEXANDRON NIMROD·Filed 2010·Granted Dec 10, 2013·0 cites·20 claims
- 1941US8595407B2Representation of data relative to varying thresholdsALEXANDRON NIMROD·Filed 2011·Granted Nov 26, 2013·0 cites·20 claims
- 2041US2013305017A1Compiled control code parallelization by hardware treatment of data dependencyRABINOVITCH ALEXANDER·Filed 2012·Application pending·0 cites
- 2141US2013298129A1Controlling a sequence of parallel executionsRABINOVITCH ALEXANDER·Filed 2012·Application pending·0 cites
- 2241US2013117532A1Interleaving address modificationRABINOVITCH ALEXANDER·Filed 2011·Application pending·0 cites
- 2340US8798129B2Biquad infinite impulse response system transformationRABINOVITCH ALEXANDER·Filed 2012·Granted Aug 5, 2014·0 cites·21 claims
- 2440US2013208796A1Cache prefetch during a hierarchical motion estimationAMITAY AMICHAY·Filed 2012·Application pending·0 cites
- 2540US2013080741A1Hardware control of instruction operands in a processorRABINOVITCH ALEXANDER·Filed 2011·Application pending·0 cites
- 2639US2012324195A1Allocation of preset cache linesRABINOVITCH ALEXANDER·Filed 2011·Application pending·0 cites
- 2739US2013113543A1Multiplication dynamic range increase by on the fly data scalingDUBROVIN LEONID·Filed 2011·Application pending·0 cites
- 2839US2013094567A1Apparatus and methods for performing block matching on a video streamAMITAY AMICHAY·Filed 2011·Application pending·0 cites
- 2939US2012151150A1Cache Line Fetching and Fetch Ahead Control Using Post Modification InformationRABINOVITCH ALEXANDER·Filed 2010·Application pending·0 cites
- 3039US2013094586A1Direct Memory Access With On-The-Fly Generation of Frame Information For Unrestricted Motion VectorsAMITAY AMICHAY·Filed 2011·Application pending·0 cites
- 3137US2013318307A1Memory mapped fetch-ahead control for data cache accessesRABINOVITCH ALEXANDER·Filed 2012·Application pending·0 cites
- 3236US8499139B2Avoiding stall in processor pipeline upon read after write resource conflict when intervening write presentDUBROVIN LEONID·Filed 2010·Granted Jul 30, 2013·0 cites·20 claims
- 3331US2013046961A1Speculative memory write in a pipelined processorRABINOVITCH ALEXANDER·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →