Inventor · disambiguated record
Benjamin Herrenschmidt
Also filed as: HERRENSCHMIDT BENJAMIN
21 granted patents·1 pending application·116 citations·filing 2005–2021
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
22 records- 0193US10387686B2Hardware based isolation for secure execution of virtual machinesIBM·Filed 2017·Granted Aug 20, 2019·11 cites·24 claims
- 0292US9323692B2Managing translation of a same address across multiple contexts using a same entry in a translation lookaside bufferIBM·Filed 2014·Granted Apr 26, 2016·15 cites·13 claims
- 0392US9317443B2Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spacesIBM·Filed 2014·Granted Apr 19, 2016·17 cites·12 claims
- 0489US8364933B2Software assisted translation lookaside buffer search mechanismIBM·Filed 2009·Granted Jan 29, 2013·31 cites·16 claims
- 0585US8688953B2Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entitiesFRANKE HUBERTUS·Filed 2012·Granted Apr 1, 2014·8 cites·23 claims
- 0684US9417846B1Techniques for improving random number generation securityIBM·Filed 2015·Granted Aug 16, 2016·4 cites·8 claims
- 0783US10817434B2Interruptible translation entry invalidation in a multithreaded data processing systemIBM·Filed 2018·Granted Oct 27, 2020·3 cites·16 claims
- 0879US9330023B2Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spacesIBM·Filed 2014·Granted May 3, 2016·4 cites·8 claims
- 0978US8275971B2Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entitiesFRANKE HUBERTUS·Filed 2008·Granted Sep 25, 2012·8 cites·20 claims
- 1076US8296547B2Loading entries into a TLB in hardware via indirect TLB entriesHEIL TIMOTHY H·Filed 2009·Granted Oct 23, 2012·8 cites·15 claims
- 1173US11226902B2Translation load instruction with access protectionIBM·Filed 2019·Granted Jan 18, 2022·1 cites·22 claims
- 1268US9251088B2Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidationIBM·Filed 2013·Granted Feb 2, 2016·2 cites·20 claims
- 1367US9575728B1Random number generation securityIBM·Filed 2016·Granted Feb 21, 2017·1 cites·12 claims
- 1466US9626187B2Transactional memory system supporting unbroken suspended executionCAIN III HAROLD W·Filed 2010·Granted Apr 18, 2017·2 cites·21 claims
- 1565US9311249B2Managing translation of a same address across multiple contexts using a same entry in a translation lookaside bufferIBM·Filed 2014·Granted Apr 12, 2016·1 cites·7 claims
- 1654US10255194B2Configurable I/O address translation data structureIBM·Filed 2013·Granted Apr 9, 2019·0 cites·4 claims
- 1752US10241923B2Configurable I/O address translation data structureIBM·Filed 2012·Granted Mar 26, 2019·0 cites·12 claims
- 1851US11755362B2Techniques for handling escalation of interrupts in a data processing systemIBM·Filed 2021·Granted Sep 12, 2023·0 cites·18 claims
- 1948US11461474B2Process-based virtualization system for executing a secure application processIBM·Filed 2020·Granted Oct 4, 2022·0 cites·20 claims
- 2048US10776281B2Snoop invalidate filter for distributed memory management unit to reduce snoop invalidate latencyIBM·Filed 2018·Granted Sep 15, 2020·0 cites·19 claims
- 2146US11221957B2Promotion of ERAT cache entriesIBM·Filed 2018·Granted Jan 11, 2022·0 cites·18 claims
- 2240US2007124545A1Automatic yielding on lock contention for multi-threaded processorsBLANCHARD ANTON·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →