Inventor · disambiguated record
Toshiharu Asaka
Also filed as: ASAKA TOSHIHARU
8 granted patents·1 pending application·103 citations·filing 1995–2008
87Inventor score
Top patents by PatentIndex Score
9 records- 0194US7613971B2Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuitNEC ELECTRONICS CORP·Filed 2006·Granted Nov 3, 2009·43 cites·12 claims
- 0264US7681096B2Semiconductor integrated circuit, BIST circuit, design program of BIST circuit, design device of BIST circuit and test method of memoryNEC ELECTRONICS CORP·Filed 2007·Granted Mar 16, 2010·5 cites·19 claims
- 0360US8056036B2Semiconductor integrated circuit and method of designing thereof based on TPIRENESAS ELECTRONICS CORP·Filed 2008·Granted Nov 8, 2011·3 cites·16 claims
- 0459US8015462B2Test circuitRENESAS ELECTRONICS CORP·Filed 2008·Granted Sep 6, 2011·3 cites·15 claims
- 0546US2008148209A1Method of designing semiconductor integrated circuit using test point insertion adjustable to delay timeNEC ELECTRONICS CORP·Filed 2007·Application pending·0 cites
- 0644US6189128B1Design for testability method selectively employing two methods for forming scan paths in a circuitNEC CORP·Filed 1998·Granted Feb 13, 2001·12 cites·11 claims
- 0744US5721690ALogic circuit synthesisNEC CORP·Filed 1995·Granted Feb 24, 1998·19 cites·6 claims
- 0837US6070258ALogic synthesis for testability system which enables improvement in testability and effective selection of center state and logic synthesis method thereofNEC CORP·Filed 1998·Granted May 30, 2000·8 cites·22 claims
- 0936US6028988ASystem for logic synthesis-for-testability capable of improving testability for an FSM having an asynchronous reset stateNEC CORP·Filed 1997·Granted Feb 22, 2000·10 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →