Inventor · disambiguated record
Jama I. Barreh
Also filed as: BARREH JAMA · BARREH JAMA I · BARREH JAMA ISMAIL
19 granted patents·3 pending applications·337 citations·filing 2004–2021
94Inventor score
Technology areasG06F
Files withSUN MICROSYSTEMS INC5GOLLA ROBERT T4BARREH JAMA I2CADENCE DESIGN SYSTEMS INC2ORACLE AMERICA INC2
Top patents by PatentIndex Score
22 records- 0193US7185178B1Fetch speculation in a multithreaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Feb 27, 2007·90 cites·21 claims
- 0290US7434000B1Handling duplicate cache misses in a multithreaded/multi-core processorSUN MICROSYSTEMS INC·Filed 2004·Granted Oct 7, 2008·68 cites·19 claims
- 0389US8555038B2Processor and method providing instruction support for instructions that utilize multiple register windowsOLSON CHRISTOPHER H·Filed 2010·Granted Oct 8, 2013·14 cites·18 claims
- 0484US7861063B1Delay slot handling in a processorORACLE AMERICA INC·Filed 2004·Granted Dec 28, 2010·36 cites·27 claims
- 0583US7353445B1Cache error handling in a multithreaded/multi-core processorSUN MICROSYSTEMS INC·Filed 2004·Granted Apr 1, 2008·35 cites·29 claims
- 0682US8335912B2Logical map table for detecting dependency conditions between instructions having varying width operand valuesGOLLA ROBERT T·Filed 2009·Granted Dec 18, 2012·12 cites·18 claims
- 0781US8037250B1Arbitrating cache misses in a multithreaded/multi-core processorORACLE AMERICA INC·Filed 2004·Granted Oct 11, 2011·30 cites·28 claims
- 0875US8429386B2Dynamic tag allocation in a multithreaded out-of-order processorJORDAN PAUL J·Filed 2009·Granted Apr 23, 2013·7 cites·15 claims
- 0970US8904156B2Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processorSHAH MANISH K·Filed 2009·Granted Dec 2, 2014·5 cites·20 claims
- 1070US7383403B1Concurrent bypass to instruction buffers in a fine grain multithreaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Jun 3, 2008·16 cites·16 claims
- 1165US8225034B1Hybrid instruction bufferGOLLA ROBERT T·Filed 2004·Granted Jul 17, 2012·11 cites·25 claims
- 1265US7343474B1Minimal address state in a fine grain multithreaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Mar 11, 2008·10 cites·30 claims
- 1363US10860326B2Multi-threaded instruction buffer designORACLE INT CORP·Filed 2019·Granted Dec 8, 2020·0 cites·20 claims
- 1461US8504805B2Processor operating mode for mitigating dependency conditions between instructions having different operand sizesGOLLA ROBERT T·Filed 2009·Granted Aug 6, 2013·2 cites·16 claims
- 1560US9529594B2Miss buffer for a multi-threaded processorSHAH MANISH K·Filed 2010·Granted Dec 27, 2016·1 cites·18 claims
- 1655US11740973B2Instruction error handlingCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Aug 29, 2023·0 cites·19 claims
- 1755US11507414B2Circuit for fast interrupt handlingCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Nov 22, 2022·0 cites·19 claims
- 1855US11023342B2Cache diagnostic techniquesWESTERN DIGITAL TECH INC·Filed 2019·Granted Jun 1, 2021·0 cites·17 claims
- 1949US2010274961A1Physically-indexed logical map tableGOLLA ROBERT T·Filed 2009·Application pending·0 cites
- 2045US2016055001A1Low power instruction buffer for high performance processorsORACLE INT CORP·Filed 2014·Application pending·0 cites
- 2142US10346173B2Multi-threaded instruction buffer designBARREH JAMA I·Filed 2011·Granted Jul 9, 2019·0 cites·14 claims
- 2235US2013138888A1Storing a target address of a control transfer instruction in an instruction fieldBARREH JAMA I·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →