Inventor · disambiguated record
Yoshihiko Nagayasu
Also filed as: NAGAYASU YOSHIHIKO
5 granted patents·112 citations·filing 1993–2005
82Inventor score
Top patents by PatentIndex Score
5 records- 0173US5591657ASemiconductor apparatus manufacturing method employing gate side wall self-aligning for maskingFUJI ELECTRIC CO LTD·Filed 1994·Granted Jan 7, 1997·35 cites·24 claims
- 0270US7510975B2Method for manufacturing a semiconductor device having trenches defined in the substrate surfaceFUJI ELECTRIC HOLDINGS·Filed 2005·Granted Mar 31, 2009·6 cites·14 claims
- 0369US5340756AMethod for producing self-aligned LDD CMOS, DMOS with deeper source/drain and P-base regions and, bipolar devices on a common substrateFUJI ELECTRIC CO LTD·Filed 1993·Granted Aug 23, 1994·33 cites·7 claims
- 0457US6087688AField effect transistorFUJI ELECTRIC CO LTD·Filed 1999·Granted Jul 11, 2000·17 cites·16 claims
- 0552US5972768AMethod of manufacturing semiconductor device having low contact resistanceFUJI ELECTRIC CO LTD·Filed 1997·Granted Oct 26, 1999·21 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →