Inventor · disambiguated record
Raymond Cheung Yeung
Also filed as: YEUNG RAYMOND C · YEUNG RAYMOND CHEUNG
18 granted patents·4 pending applications·212 citations·filing 2002–2011
94Inventor score
Top patents by PatentIndex Score
22 records- 0193US7395414B2Dynamic recalculation of resource vector at issue queue for steering of dependent instructionsIBM·Filed 2005·Granted Jul 1, 2008·31 cites·6 claims
- 0290US7627742B2Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling systemIBM·Filed 2007·Granted Dec 1, 2009·27 cites·17 claims
- 0389US7669038B2Method and apparatus for back to back issue of dependent instructions in an out of order issue queueIBM·Filed 2008·Granted Feb 23, 2010·18 cites·10 claims
- 0483US7631308B2Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessorsIBM·Filed 2005·Granted Dec 8, 2009·12 cites·3 claims
- 0583US7093106B2Register rename array with individual thread bits set upon allocation and cleared upon instruction completionIBM·Filed 2003·Granted Aug 15, 2006·43 cites·23 claims
- 0683US7000047B2Mechanism for effectively handling livelocks in a simultaneous multithreading processorIBM·Filed 2003·Granted Feb 14, 2006·36 cites·26 claims
- 0780US8397190B2Method for manipulating and repartitioning a hierarchical integrated circuit designKENNEY ROBERT D·Filed 2011·Granted Mar 12, 2013·7 cites·25 claims
- 0879US8006070B2Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling systemIBM·Filed 2007·Granted Aug 23, 2011·9 cites·20 claims
- 0977US8255669B2Method and apparatus for thread priority control in a multi-threaded processor based upon branch issue information including branch confidence informationGSCHWIND MICHAEL KARL·Filed 2008·Granted Aug 28, 2012·8 cites·9 claims
- 1077US7925853B2Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling systemIBM·Filed 2008·Granted Apr 12, 2011·8 cites·20 claims
- 1174US8418180B2Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessorsBISHOP JAMES WILSON·Filed 2008·Granted Apr 9, 2013·6 cites·14 claims
- 1267US7380104B2Method and apparatus for back to back issue of dependent instructions in an out of order issue queueIBM·Filed 2006·Granted May 27, 2008·3 cites·10 claims
- 1360US8429580B2Method for preparing for and formally verifying a modified integrated circuit designYEUNG RAYMOND C·Filed 2011·Granted Apr 23, 2013·2 cites·14 claims
- 1455US8768989B2Funnel shifter implementationYEUNG RAYMOND C·Filed 2011·Granted Jul 1, 2014·2 cites·23 claims
- 1553US7650486B2Dynamic recalculation of resource vector at issue queue for steering of dependent instructionsIBM·Filed 2008·Granted Jan 19, 2010·0 cites·6 claims
- 1647US2009193240A1Method and apparatus for increasing thread priority in response to flush information in a multi-threaded processor of an information handling systemIBM·Filed 2008·Application pending·0 cites
- 1744US7490226B2Method using vector component comprising first and second bits to regulate movement of dependent instructions in a microprocessorIBM·Filed 2005·Granted Feb 10, 2009·0 cites·18 claims
- 1843US7188233B2System and method for performing floating point store foldingIBM·Filed 2005·Granted Mar 6, 2007·0 cites·16 claims
- 1942US2006179286A1System and method for processing limited out-of-order execution of floating point loadsIBM·Filed 2005·Application pending·0 cites
- 2042US2003182537A1Mechanism to assign more logical load/store tags than available physical registers in a microprocessor systemIBM·Filed 2002·Application pending·0 cites
- 2141US2006168393A1Apparatus and method for dependency tracking and register file bypass controls using a scannable register fileCHRISTENSEN BJORN P·Filed 2005·Application pending·0 cites
- 2238US8482315B2One-of-n N-nary logic implementation of a storage cellSENINGEN MICHAEL R·Filed 2011·Granted Jul 9, 2013·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →