Inventor · disambiguated record
Nazar Zaidi
Also filed as: ZAIDI NAZAR · ZAIDI NAZAR A · ZAIDI NAZAR ABBAS
47 granted patents·1 pending application·1,568 citations·filing 1996–2013
99Inventor score
Top patents by PatentIndex Score
48 records- 0198US6880049B2Sharing a second tier cache memory in a multi-processorJUNIPER NETWORKS INC·Filed 2002·Granted Apr 12, 2005·139 cites·23 claims
- 0297US7184446B2Cross-bar switch employing a multiple entry point FIFOJUNIPER NETWORKS INC·Filed 2001·Granted Feb 27, 2007·109 cites·39 claims
- 0396US7765328B2Content service aggregation systemJUNIPER NETWORKS INC·Filed 2007·Granted Jul 27, 2010·106 cites·23 claims
- 0494US8370528B2Content service aggregation systemJUNIPER NETWORKS INC·Filed 2010·Granted Feb 5, 2013·33 cites·9 claims
- 0594US7305492B2Content service aggregation systemJUNIPER NETWORKS INC·Filed 2002·Granted Dec 4, 2007·121 cites·26 claims
- 0691US6895477B2Ring-based memory requests in a shared memory multi-processorJUNIPER NETWORKS INC·Filed 2002·Granted May 17, 2005·43 cites·25 claims
- 0790US6901482B2Managing ownership of a full cache line using a store-create operationJUNIPER NETWORKS INC·Filed 2002·Granted May 31, 2005·40 cites·24 claims
- 0889US7363353B2Content service aggregation device for a data centerJUNIPER NETWORKS INC·Filed 2002·Granted Apr 22, 2008·82 cites·31 claims
- 0989US6065105ADependency matrixINTEL CORP·Filed 1997·Granted May 16, 2000·169 cites·16 claims
- 1088US6745289B2Processing packets in cache memoryJUNIPER NETWORKS INC·Filed 2002·Granted Jun 1, 2004·31 cites·37 claims
- 1187US6839808B2Processing cluster having multiple compute engines and shared tier one cachesJUNIPER NETWORKS INC·Filed 2001·Granted Jan 4, 2005·35 cites·41 claims
- 1287US6016540AMethod and apparatus for scheduling instructions in wavesINTEL CORP·Filed 1997·Granted Jan 18, 2000·136 cites·18 claims
- 1385US7392369B2Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation checkINTEL CORP·Filed 2006·Granted Jun 24, 2008·14 cites·24 claims
- 1485US6892282B2Ring based multi-processing systemJUNIPER NETWORKS INC·Filed 2002·Granted May 10, 2005·22 cites·33 claims
- 1582US6920542B2Application processing employing a coprocessorJUNIPER NETWORKS INC·Filed 2002·Granted Jul 19, 2005·17 cites·49 claims
- 1679US9083628B2Content service aggregation systemJUNIPER NETWORKS INC·Filed 2013·Granted Jul 14, 2015·4 cites·19 claims
- 1778US7353368B2Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point supportINTEL CORP·Filed 2000·Granted Apr 1, 2008·27 cites·16 claims
- 1877US7068603B2Cross-bar switchJUNIPER NETWORKS INC·Filed 2001·Granted Jun 27, 2006·13 cites·40 claims
- 1975US5961630AMethod and apparatus for handling dynamic structural hazards and exceptions by using post-ready latencyINTEL CORP·Filed 1997·Granted Oct 5, 1999·70 cites·21 claims
- 2073US6898673B2Co-processor including a media access controllerJUNIPER NETWORKS INC·Filed 2002·Granted May 24, 2005·8 cites·31 claims
- 2171US7103058B2Cross-bar switch with explicit multicast supportJUNIPER NETWORKS INC·Filed 2001·Granted Sep 5, 2006·8 cites·34 claims
- 2271US6542981B1Microcode upgrade and special function support by executing RISC instruction to invoke resident microcodeINTEL CORP·Filed 1999·Granted Apr 1, 2003·57 cites·24 claims
- 2370US7330963B2Resolving all previous potentially excepting architectural operations before issuing store architectural operationINTEL CORP·Filed 2006·Granted Feb 12, 2008·4 cites·11 claims
- 2469US7065090B2Cross-bar switch supporting implicit multicast addressingJUNIPER NETWORKS INC·Filed 2001·Granted Jun 20, 2006·7 cites·34 claims
- 2569US6581154B1Expanding microcode associated with full and partial width macroinstructionsINTEL CORP·Filed 1999·Granted Jun 17, 2003·52 cites·14 claims
- 2665US7062636B2Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operationINTEL CORP·Filed 2002·Granted Jun 13, 2006·9 cites·14 claims
- 2765US5996064AMethod and apparatus for guaranteeing minimum variable schedule distance by using post-ready latencyINTEL CORP·Filed 1997·Granted Nov 30, 1999·44 cites·22 claims
- 2863US7170902B2Cross-bar switch incorporating a sink port with retry capabilityJUNIPER NETWORKS INC·Filed 2001·Granted Jan 30, 2007·4 cites·18 claims
- 2963US7123585B2Cross-bar switch with bandwidth allocationJUNIPER NETWORKS INC·Filed 2001·Granted Oct 17, 2006·4 cites·32 claims
- 3063US7082139B2Cross-bar switch with sink port accepting multiple packetsJUNIPER NETWORKS INC·Filed 2001·Granted Jul 25, 2006·4 cites·28 claims
- 3156US6574689B1Method and apparatus for live-lock preventionINTEL CORP·Filed 2000·Granted Jun 3, 2003·5 cites·12 claims
- 3255US7733905B2Cross-bar switch having bandwidth allocationJUNIPER NETWORKS INC·Filed 2007·Granted Jun 8, 2010·0 cites·10 claims
- 3355US5918031AComputer utilizing special micro-operations for encoding of multiple variant code flowsINTEL CORP·Filed 1996·Granted Jun 29, 1999·34 cites·25 claims
- 3454US7813364B2Cross-bar switch incorporating a sink port with retry capabilityJUNIPER NETWORKS INC·Filed 2006·Granted Oct 12, 2010·0 cites·11 claims
- 3548US6032250AMethod and apparatus for identifying instruction boundariesINTEL CORP·Filed 1997·Granted Feb 29, 2000·20 cites·24 claims
- 3645US2004103248A1Advanced telecommunications processorFiled 2003·Application pending·0 cites
- 3743US5944818AMethod and apparatus for accelerated instruction restart in a microprocessorINTEL CORP·Filed 1996·Granted Aug 31, 1999·17 cites·17 claims
- 3842US6292882B1Method and apparatus for filtering valid information for downstream processingINTEL CORP·Filed 1998·Granted Sep 18, 2001·13 cites·30 claims
- 3942US6055652AMultiple segment register use with different operand sizeINTEL CORP·Filed 1999·Granted Apr 25, 2000·11 cites·18 claims
- 4036US6405307B1Apparatus and method for detecting and handling self-modifying code conflicts in an instruction fetch pipelineINTEL CORP·Filed 1998·Granted Jun 11, 2002·9 cites·25 claims
- 4136US6049897AMultiple segment register use with different operand sizeINTEL CORP·Filed 1997·Granted Apr 11, 2000·7 cites·7 claims
- 4235US6044456AElectronic system and method for maintaining synchronization of multiple front-end pipelinesINTEL CORP·Filed 1998·Granted Mar 28, 2000·11 cites·25 claims
- 4335US5961615AMethod and apparatus for queuing dataINTEL CORP·Filed 1997·Granted Oct 5, 1999·8 cites·14 claims
- 4435US5954814ASystem for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a pipelineINTEL CORP·Filed 1997·Granted Sep 21, 1999·7 cites·12 claims
- 4532US6237088B1System and method for tracking in-flight instructions in a pipelineINTEL CORP·Filed 1998·Granted May 22, 2001·3 cites·22 claims
- 4631US6363408B1Method and apparatus for summing selected bits from a plurality of machine vectorsINTEL CORP·Filed 1998·Granted Mar 26, 2002·2 cites·30 claims
- 4731US6216221B1Method and apparatus for expanding instructionsINTEL CORP·Filed 1997·Granted Apr 10, 2001·4 cites·29 claims
- 4830US6523106B1Method and apparatus for efficient pipeliningINTEL CORP·Filed 1998·Granted Feb 18, 2003·5 cites·15 claims
Join the waitlist — get patent alerts
Get an alert when Nazar Zaidi files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →