Inventor · disambiguated record
Chu-Wei Hu
Also filed as: HU CHU-WEI
19 granted patents·5 pending applications·248 citations·filing 1998–2025
94Inventor score
Top patents by PatentIndex Score
24 records- 0191US6444544B1Method of forming an aluminum protection guard structure for a copper metal structureTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Sep 3, 2002·76 cites·23 claims
- 0279US6451679B1Ion mixing between two-step titanium deposition process for titanium salicide CMOS technologyTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Sep 17, 2002·32 cites·34 claims
- 0374US9123558B2Bipolar junction transistorFAN SHENG-HUNG·Filed 2011·Granted Sep 1, 2015·7 cites·20 claims
- 0473US6287926B1Self aligned channel implant, elevated S/D process by gate electrode damasceneTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Sep 11, 2001·36 cites·10 claims
- 0567US6211069B1Dual damascene process flow for a deep sub-micron technologyTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Apr 3, 2001·37 cites·12 claims
- 0666US10418480B2Semiconductor device capable of high-voltage operationMEDIATEK INC·Filed 2017·Granted Sep 17, 2019·1 cites·24 claims
- 0765US11728320B2Semiconductor packageMEDIATEK INC·Filed 2022·Granted Aug 15, 2023·0 cites·20 claims
- 0865US6583017B2Self aligned channel implant, elevated S/D process by gate electrode damasceneTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jun 24, 2003·8 cites·9 claims
- 0964US9379175B2Integrated circuits and fabrication methods thereofMEDIATEK INC·Filed 2014·Granted Jun 28, 2016·1 cites·12 claims
- 1059US11342316B2Semiconductor packageMEDIATEK INC·Filed 2020·Granted May 24, 2022·0 cites·20 claims
- 1158US2025218875A1Semiconductor deviceMEDIATEK INC·Filed 2024·Application pending·0 cites
- 1258US2025174557A1Semiconductor die having a die damage ring and fabrication method thereofMEDIATEK INC·Filed 2024·Application pending·0 cites
- 1357US6169003B1Method for forming a MOS device with an elevated source and drain, and having a self-aligned channel inputTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jan 2, 2001·20 cites·15 claims
- 1457US2025174500A1Semiconductor package with system test ringMEDIATEK INC·Filed 2024·Application pending·0 cites
- 1555US9793337B2Integrated circuits and fabrication methods thereofMEDIATEK INC·Filed 2016·Granted Oct 17, 2017·0 cites·21 claims
- 1654US2023260894A1Semiconductor device with integrated deep trench capacitorsMEDIATEK INC·Filed 2023·Application pending·0 cites
- 1753US9508786B2Integrated circuits and fabrication methods thereofMEDIATEK INC·Filed 2015·Granted Nov 29, 2016·0 cites·15 claims
- 1853US6207538B1Method for forming n and p wells in a semiconductor substrate using a single masking stepTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Mar 27, 2001·14 cites·17 claims
- 1950US6790756B2Self aligned channel implant, elevated S/D process by gate electrode damasceneTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Sep 14, 2004·2 cites·8 claims
- 2044US6074905AFormation of a thin oxide protection layer at poly sidewall and area surfaceTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jun 13, 2000·11 cites·22 claims
- 2144US2025253267A1Semiconductor deviceMEDIATEK INC·Filed 2025·Application pending·0 cites
- 2238US6787470B2Sacrificial feature for corrosion prevention during CMPTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Sep 7, 2004·0 cites·17 claims
- 2334US6951803B2Method to prevent passivation layer peeling in a solder bump formation processTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 4, 2005·3 cites·20 claims
- 2428US8932937B2Photoresist mask-free oxide define region (ODR)LEE CHU-SHENG·Filed 2002·Granted Jan 13, 2015·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →