Inventor · disambiguated record
Ricardo H. Bruce
Also filed as: BRUCE RICARDO · BRUCE RICARDO H
30 granted patents·2 pending applications·2,441 citations·filing 1997–2025
98Inventor score
Top patents by PatentIndex Score
32 records- 0198US6000006AUnified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storageBIT MICROSYSTEMS INC·Filed 1997·Granted Dec 7, 1999·1k cites·19 claims
- 0295US8788725B2Multilevel memory bus system for solid-state mass storageBITMICRO NETWORKS INC·Filed 2013·Granted Jul 22, 2014·41 cites·27 claims
- 0395US8447908B2Multilevel memory bus system for solid-state mass storageBRUCE RICARDO H·Filed 2010·Granted May 21, 2013·73 cites·29 claims
- 0495US5822251AExpandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllersBIT MICROSYSTEMS INC·Filed 1997·Granted Oct 13, 1998·302 cites·24 claims
- 0594US8959307B1Reduced latency memory read transactions in storage devicesBRUCE REY H·Filed 2008·Granted Feb 17, 2015·81 cites·37 claims
- 0694US6970890B1Method and apparatus for data recoveryBITMICRO NETWORKS INC·Filed 2001·Granted Nov 29, 2005·102 cites·31 claims
- 0794US5956743ATransparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operationsBIT MICROSYSTEMS INC·Filed 1997·Granted Sep 21, 1999·258 cites·20 claims
- 0893US6529416B2Parallel erase operations in memory systemsBITMICRO NETWORKS INC·Filed 2001·Granted Mar 4, 2003·71 cites·20 claims
- 0992US9952991B1Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operationBITMICRO NETWORKS INC·Filed 2015·Granted Apr 24, 2018·16 cites·17 claims
- 1092US7620748B1Hardware assisted non-volatile memory-to-input/output direct memory access (DMA) transferBITMICRO NETWORKS INC·Filed 2006·Granted Nov 17, 2009·89 cites·13 claims
- 1189US10552050B1Multi-dimensional computer storage systemBITMICRO LLC·Filed 2017·Granted Feb 4, 2020·7 cites·13 claims
- 1289US9135190B1Multi-profile memory controller for computing devicesBRUCE RICARDO H·Filed 2010·Granted Sep 15, 2015·52 cites·101 claims
- 1389US6981070B1Network storage device having solid-state non-volatile memoryLUK SHUN HANG·Filed 2001·Granted Dec 27, 2005·143 cites·5 claims
- 1487US7729370B1Apparatus for networking devices having fibre channel node functionalityBITMICRO NETWORKS INC·Filed 2006·Granted Jun 1, 2010·32 cites·49 claims
- 1586US10120586B1Memory transaction with reduced latencyBITMICRO LLC·Filed 2015·Granted Nov 6, 2018·6 cites·23 claims
- 1686US9501436B1Multi-level message passing descriptorBITMICRO NETWORKS INC·Filed 2014·Granted Nov 22, 2016·12 cites·18 claims
- 1785US10877907B2Multilevel memory bus systemBITMICRO LLC·Filed 2018·Granted Dec 29, 2020·3 cites·17 claims
- 1884US10489318B1Scatter-gather approach for parallel data transfer in a mass storage systemBITMICRO NETWORKS INC·Filed 2015·Granted Nov 26, 2019·6 cites·16 claims
- 1983US9971524B1Scatter-gather approach for parallel data transfer in a mass storage systemBITMICRO NETWORKS INC·Filed 2014·Granted May 15, 2018·10 cites·20 claims
- 2082US8093103B2Multiple chip module and package stacking method for storage devicesBRUCE REY H·Filed 2010·Granted Jan 10, 2012·7 cites·16 claims
- 2180US7826243B2Multiple chip module and package stacking for storage devicesBITMICRO NETWORKS INC·Filed 2005·Granted Nov 2, 2010·10 cites·15 claims
- 2278US9798688B1Bus arbitration with routing and failover mechanismBITMICRO NETWORKS INC·Filed 2014·Granted Oct 24, 2017·5 cites·20 claims
- 2375US6496939B2Method and system for controlling data in a computer system in the event of a power failureBIT MICROSYSTEMS INC·Filed 1999·Granted Dec 17, 2002·79 cites·28 claims
- 2470US10459842B1Data storage system with configurable prefetch buffersBITMICRO NETWORKS INC·Filed 2018·Granted Oct 29, 2019·1 cites·20 claims
- 2570US9916213B1Bus arbitration with routing and failover mechanismBITMICRO NETWORKS INC·Filed 2015·Granted Mar 13, 2018·2 cites·17 claims
- 2667US10013373B1Multi-level message passing descriptorBITMICRO NETWORKS INC·Filed 2016·Granted Jul 3, 2018·1 cites·20 claims
- 2766US9875205B1Network of memory systemsBITMICRO NETWORKS INC·Filed 2014·Granted Jan 23, 2018·2 cites·20 claims
- 2856US10133686B2Multilevel memory bus systemBITMICRO LLC·Filed 2014·Granted Nov 20, 2018·0 cites·36 claims
- 2954US10423554B1Bus arbitration with routing and failover mechanismBITMICRO NETWORKS INC·Filed 2017·Granted Sep 24, 2019·0 cites·21 claims
- 3053US2025278197A1Redundant array of independent serversDEEPLY HUMAN INC·Filed 2025·Application pending·0 cites
- 3149US10430303B1Bus arbitration with routing and failover mechanismBITMICRO NETWORKS INC·Filed 2018·Granted Oct 1, 2019·0 cites·22 claims
- 3244US2002141244A1Parallel erase operations in memory systemsFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →