Inventor · disambiguated record
Tin H. Lai
Also filed as: LAI TIN · LAI TIN H
25 granted patents·218 citations·filing 2000–2012
96Inventor score
Top patents by PatentIndex Score
25 records- 0193US7782935B1Half-rate DFE with duplicate path for high data-rate operationALTERA CORP·Filed 2006·Granted Aug 24, 2010·28 cites·21 claims
- 0293US7541857B1Comparator offset cancellation assisted by PLD resourcesALTERA CORP·Filed 2005·Granted Jun 2, 2009·29 cites·26 claims
- 0393US7514968B1H-tree driver circuitryALTERA CORP·Filed 2007·Granted Apr 7, 2009·25 cites·15 claims
- 0493US7368968B1Signal offset cancellationALTERA CORP·Filed 2005·Granted May 6, 2008·21 cites·17 claims
- 0588US7336211B1Resistance compensated DAC ladderALTERA CORP·Filed 2006·Granted Feb 26, 2008·20 cites·21 claims
- 0685US8175143B1Adaptive equalization using data level detectionWONG WILSON·Filed 2008·Granted May 8, 2012·14 cites·26 claims
- 0779US7590174B2Signal adjustment receiver circuitryALTERA CORP·Filed 2005·Granted Sep 15, 2009·6 cites·10 claims
- 0878US7710180B1Signal offset cancellationALTERA CORP·Filed 2008·Granted May 4, 2010·7 cites·20 claims
- 0977US8063807B1Equalization circuitry including a digital-to-analog converter having a voltage divider and a multiplexerLAI TIN H·Filed 2009·Granted Nov 22, 2011·7 cites·24 claims
- 1077US6593772B2Embedded memory blocks for programmable logicALTERA CORP·Filed 2002·Granted Jul 15, 2003·16 cites·29 claims
- 1176US8416898B1Techniques for decision feedback equalization that reduce variations in the tap weightLUO MEI·Filed 2009·Granted Apr 9, 2013·7 cites·21 claims
- 1276US6486702B1Embedded memory blocks for programmable logicALTERA CORP·Filed 2000·Granted Nov 26, 2002·16 cites·25 claims
- 1375US8829958B2Clock and data recovery circuitry with auto-speed negotiation and other possible featuresALTERA CORP·Filed 2012·Granted Sep 9, 2014·3 cites·7 claims
- 1475US8811555B2Clock and data recovery circuitry with auto-speed negotiation and other possible featuresASADUZZAMAN KAZI·Filed 2010·Granted Aug 19, 2014·5 cites·14 claims
- 1572US7920621B2Digital adaptation circuitry and methods for programmable logic devicesALTERA CORP·Filed 2006·Granted Apr 5, 2011·4 cites·23 claims
- 1670US7760799B2Programmable digital equalization control circuitry and methodsALTERA CORP·Filed 2005·Granted Jul 20, 2010·4 cites·23 claims
- 1761US7733997B2Signal adjustment receiver circuitryALTERA CORP·Filed 2006·Granted Jun 8, 2010·1 cites·19 claims
- 1856US7324031B1Dynamic bias circuitALTERA CORP·Filed 2006·Granted Jan 29, 2008·2 cites·24 claims
- 1955US8208528B1Programmable adaptation convergence detectionLAI TIN H·Filed 2007·Granted Jun 26, 2012·1 cites·14 claims
- 2055US7733982B2Signal adjustment receiver circuitryALTERA CORP·Filed 2009·Granted Jun 8, 2010·0 cites·5 claims
- 2147US8098087B1Method and apparatus for standby voltage offset cancellationLAM JOHN DUNG-NGOC·Filed 2007·Granted Jan 17, 2012·2 cites·18 claims
- 2244US8208523B2Digital adaptation circuitry and methods for programmable logic devicesWONG WILSON·Filed 2011·Granted Jun 26, 2012·0 cites·19 claims
- 2344US7898313B1Signal offset cancellationALTERA CORP·Filed 2010·Granted Mar 1, 2011·0 cites·4 claims
- 2442US7358883B1Dynamic bias circuitALTERA CORP·Filed 2006·Granted Apr 15, 2008·0 cites·20 claims
- 2541US7414559B2Dynamic bias circuitALTERA CORP·Filed 2007·Granted Aug 19, 2008·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →